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Songwei Chaijiegan0107
Songwei Chai
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jiegan0107
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FROMLIST: coresight-tgu: Add signal priority support
Like circuit of a Logic analyzer, in TGU, the requirement could be configured in each step and the trigger will be created once the requirements are met. Add priority functionality here to sort the signals into different priorities. The signal which is wanted could be configured in each step's priority node, the larger number means the higher priority and the signal with higher priority will be sensed more preferentially. Link: https://lore.kernel.org/all/20250423-tgu_patch-v5-3-3b52c105cc63@quicinc.com/ Signed-off-by: Songwei Chai <quic_songchai@quicinc.com>
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3 files changed

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‎Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,3 +7,10 @@ Description:
77
Accepts only one of the 2 values - 0 or 1.
88
0 : disable TGU.
99
1 : enable TGU.
10+
11+
What: /sys/bus/coresight/devices/<tgu-name>/step[0:7]_priority[0:3]/reg[0:17]
12+
Date: February 2025
13+
KernelVersion 6.15
14+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Sam Chai (QUIC) <quic_songchai@quicinc.com>
15+
Description:
16+
(RW) Set/Get the sensed signal with specific step and priority for TGU.

‎drivers/hwtracing/coresight/coresight-tgu.c‎

Lines changed: 163 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,14 +17,128 @@
1717

1818
DEFINE_CORESIGHT_DEVLIST(tgu_devs, "tgu");
1919

20+
static int calculate_array_location(struct tgu_drvdata *drvdata,
21+
int step_index, int operation_index,
22+
int reg_index)
23+
{
24+
int ret;
25+
26+
ret = operation_index * (drvdata->max_step) *
27+
(drvdata->max_reg) +
28+
step_index * (drvdata->max_reg) + reg_index;
29+
30+
return ret;
31+
}
32+
33+
static ssize_t tgu_dataset_show(struct device *dev,
34+
struct device_attribute *attr, char *buf)
35+
{
36+
struct tgu_drvdata *drvdata = dev_get_drvdata(dev->parent);
37+
struct tgu_attribute *tgu_attr =
38+
container_of(attr, struct tgu_attribute, attr);
39+
40+
return sysfs_emit(buf, "0x%x\n",
41+
drvdata->value_table->priority[
42+
calculate_array_location(
43+
drvdata, tgu_attr->step_index,
44+
tgu_attr->operation_index,
45+
tgu_attr->reg_num)]);
46+
}
47+
48+
static ssize_t tgu_dataset_store(struct device *dev,
49+
struct device_attribute *attr,
50+
const char *buf,
51+
size_t size)
52+
{
53+
unsigned long val;
54+
55+
struct tgu_drvdata *tgu_drvdata = dev_get_drvdata(dev->parent);
56+
struct tgu_attribute *tgu_attr =
57+
container_of(attr, struct tgu_attribute, attr);
58+
59+
if (kstrtoul(buf, 0, &val))
60+
return -EINVAL;
61+
62+
guard(spinlock)(&tgu_drvdata->spinlock);
63+
tgu_drvdata->value_table->priority[calculate_array_location(
64+
tgu_drvdata, tgu_attr->step_index, tgu_attr->operation_index,
65+
tgu_attr->reg_num)] = val;
66+
67+
return size;
68+
}
69+
70+
static umode_t tgu_node_visible(struct kobject *kobject,
71+
struct attribute *attr,
72+
int n)
73+
{
74+
struct device *dev = kobj_to_dev(kobject);
75+
struct tgu_drvdata *drvdata = dev_get_drvdata(dev->parent);
76+
int ret = SYSFS_GROUP_INVISIBLE;
77+
78+
struct device_attribute *dev_attr =
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container_of(attr, struct device_attribute, attr);
80+
struct tgu_attribute *tgu_attr =
81+
container_of(dev_attr, struct tgu_attribute, attr);
82+
83+
if (tgu_attr->step_index < drvdata->max_step) {
84+
ret = (tgu_attr->reg_num < drvdata->max_reg) ?
85+
attr->mode :
86+
0;
87+
}
88+
return ret;
89+
}
90+
2091
static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata)
2192
{
93+
int i, j, k;
94+
2295
CS_UNLOCK(drvdata->base);
96+
97+
for (i = 0; i < drvdata->max_step; i++) {
98+
for (j = 0; j < MAX_PRIORITY; j++) {
99+
for (k = 0; k < drvdata->max_reg; k++) {
100+
tgu_writel(drvdata,
101+
drvdata->value_table->priority
102+
[calculate_array_location(
103+
drvdata, i, j, k)],
104+
PRIORITY_REG_STEP(i, j, k));
105+
}
106+
}
107+
}
108+
23109
/* Enable TGU to program the triggers */
24110
tgu_writel(drvdata, 1, TGU_CONTROL);
25111
CS_LOCK(drvdata->base);
26112
}
27113

114+
static void tgu_set_reg_number(struct tgu_drvdata *drvdata)
115+
{
116+
int num_sense_input;
117+
int num_reg;
118+
u32 devid;
119+
120+
devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
121+
122+
num_sense_input = TGU_DEVID_SENSE_INPUT(devid);
123+
if (((num_sense_input * NUMBER_BITS_EACH_SIGNAL) % LENGTH_REGISTER) == 0)
124+
num_reg = (num_sense_input * NUMBER_BITS_EACH_SIGNAL) / LENGTH_REGISTER;
125+
else
126+
num_reg = ((num_sense_input * NUMBER_BITS_EACH_SIGNAL) / LENGTH_REGISTER) + 1;
127+
drvdata->max_reg = num_reg;
128+
}
129+
130+
static void tgu_set_steps(struct tgu_drvdata *drvdata)
131+
{
132+
int num_steps;
133+
u32 devid;
134+
135+
devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
136+
137+
num_steps = TGU_DEVID_STEPS(devid);
138+
139+
drvdata->max_step = num_steps;
140+
}
141+
28142
static int tgu_enable(struct coresight_device *csdev, enum cs_mode mode,
29143
void *data)
30144
{
@@ -125,6 +239,38 @@ static const struct attribute_group tgu_common_grp = {
125239

126240
static const struct attribute_group *tgu_attr_groups[] = {
127241
&tgu_common_grp,
242+
PRIORITY_ATTRIBUTE_GROUP_INIT(0, 0),
243+
PRIORITY_ATTRIBUTE_GROUP_INIT(0, 1),
244+
PRIORITY_ATTRIBUTE_GROUP_INIT(0, 2),
245+
PRIORITY_ATTRIBUTE_GROUP_INIT(0, 3),
246+
PRIORITY_ATTRIBUTE_GROUP_INIT(1, 0),
247+
PRIORITY_ATTRIBUTE_GROUP_INIT(1, 1),
248+
PRIORITY_ATTRIBUTE_GROUP_INIT(1, 2),
249+
PRIORITY_ATTRIBUTE_GROUP_INIT(1, 3),
250+
PRIORITY_ATTRIBUTE_GROUP_INIT(2, 0),
251+
PRIORITY_ATTRIBUTE_GROUP_INIT(2, 1),
252+
PRIORITY_ATTRIBUTE_GROUP_INIT(2, 2),
253+
PRIORITY_ATTRIBUTE_GROUP_INIT(2, 3),
254+
PRIORITY_ATTRIBUTE_GROUP_INIT(3, 0),
255+
PRIORITY_ATTRIBUTE_GROUP_INIT(3, 1),
256+
PRIORITY_ATTRIBUTE_GROUP_INIT(3, 2),
257+
PRIORITY_ATTRIBUTE_GROUP_INIT(3, 3),
258+
PRIORITY_ATTRIBUTE_GROUP_INIT(4, 0),
259+
PRIORITY_ATTRIBUTE_GROUP_INIT(4, 1),
260+
PRIORITY_ATTRIBUTE_GROUP_INIT(4, 2),
261+
PRIORITY_ATTRIBUTE_GROUP_INIT(4, 3),
262+
PRIORITY_ATTRIBUTE_GROUP_INIT(5, 0),
263+
PRIORITY_ATTRIBUTE_GROUP_INIT(5, 1),
264+
PRIORITY_ATTRIBUTE_GROUP_INIT(5, 2),
265+
PRIORITY_ATTRIBUTE_GROUP_INIT(5, 3),
266+
PRIORITY_ATTRIBUTE_GROUP_INIT(6, 0),
267+
PRIORITY_ATTRIBUTE_GROUP_INIT(6, 1),
268+
PRIORITY_ATTRIBUTE_GROUP_INIT(6, 2),
269+
PRIORITY_ATTRIBUTE_GROUP_INIT(6, 3),
270+
PRIORITY_ATTRIBUTE_GROUP_INIT(7, 0),
271+
PRIORITY_ATTRIBUTE_GROUP_INIT(7, 1),
272+
PRIORITY_ATTRIBUTE_GROUP_INIT(7, 2),
273+
PRIORITY_ATTRIBUTE_GROUP_INIT(7, 3),
128274
NULL,
129275
};
130276

@@ -159,6 +305,23 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id)
159305

160306
spin_lock_init(&drvdata->spinlock);
161307

308+
tgu_set_reg_number(drvdata);
309+
tgu_set_steps(drvdata);
310+
311+
drvdata->value_table =
312+
devm_kzalloc(dev, sizeof(*drvdata->value_table), GFP_KERNEL);
313+
if (!drvdata->value_table)
314+
return -ENOMEM;
315+
316+
drvdata->value_table->priority = devm_kzalloc(
317+
dev,
318+
MAX_PRIORITY * drvdata->max_reg * drvdata->max_step *
319+
sizeof(*(drvdata->value_table->priority)),
320+
GFP_KERNEL);
321+
322+
if (!drvdata->value_table->priority)
323+
return -ENOMEM;
324+
162325
drvdata->enable = false;
163326
desc.type = CORESIGHT_DEV_TYPE_HELPER;
164327
desc.pdata = adev->dev.platform_data;

‎drivers/hwtracing/coresight/coresight-tgu.h‎

Lines changed: 112 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,13 +13,122 @@
1313
#define tgu_writel(drvdata, val, off) __raw_writel((val), drvdata->base + off)
1414
#define tgu_readl(drvdata, off) __raw_readl(drvdata->base + off)
1515

16+
#define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17))
17+
#define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6))
18+
#define NUMBER_BITS_EACH_SIGNAL 4
19+
#define LENGTH_REGISTER 32
20+
21+
/*
22+
* TGU configuration space Step configuration
23+
* offset table space layout
24+
* x-------------------------x$ x-------------x$
25+
* | |$ | |$
26+
* | | | reserve |$
27+
* | | | |$
28+
* |coresight management | |-------------|base+n*0x1D8+0x1F4$
29+
* | registe | |---> |prioroty[3] |$
30+
* | | | |-------------|base+n*0x1D8+0x194$
31+
* | | | |prioroty[2] |$
32+
* |-------------------------| | |-------------|base+n*0x1D8+0x134$
33+
* | | | |prioroty[1] |$
34+
* | step[7] | | |-------------|base+n*0x1D8+0xD4$
35+
* |-------------------------|->base+0x40+7*0x1D8 | |prioroty[0] |$
36+
* | | | |-------------|base+n*0x1D8+0x74$
37+
* | ... | | | condition |$
38+
* | | | | select |$
39+
* |-------------------------|->base+0x40+1*0x1D8 | |-------------|base+n*0x1D8+0x60$
40+
* | | | | condition |$
41+
* | step[0] |--------------------> | decode |$
42+
* |-------------------------|-> base+0x40 |-------------|base+n*0x1D8+0x50$
43+
* | | | |$
44+
* | Control and status space| |Timer/Counter|$
45+
* | space | | |$
46+
* x-------------------------x->base x-------------x base+n*0x1D8+0x40$
47+
*
48+
*/
49+
#define STEP_OFFSET 0x1D8
50+
#define PRIORITY_START_OFFSET 0x0074
51+
#define PRIORITY_OFFSET 0x60
52+
#define REG_OFFSET 0x4
53+
54+
/* Calculate compare step addresses */
55+
#define PRIORITY_REG_STEP(step, priority, reg)\
56+
(PRIORITY_START_OFFSET + PRIORITY_OFFSET * priority +\
57+
REG_OFFSET * reg + STEP_OFFSET * step)
58+
59+
#define tgu_dataset_rw(name, step_index, type, reg_num) \
60+
(&((struct tgu_attribute[]){ { \
61+
__ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \
62+
step_index, \
63+
type, \
64+
reg_num, \
65+
} })[0].attr.attr)
66+
67+
#define STEP_PRIORITY(step_index, reg_num, priority) \
68+
tgu_dataset_rw(reg##reg_num, step_index, TGU_PRIORITY##priority, \
69+
reg_num)
70+
71+
#define STEP_PRIORITY_LIST(step_index, priority) \
72+
{STEP_PRIORITY(step_index, 0, priority), \
73+
STEP_PRIORITY(step_index, 1, priority), \
74+
STEP_PRIORITY(step_index, 2, priority), \
75+
STEP_PRIORITY(step_index, 3, priority), \
76+
STEP_PRIORITY(step_index, 4, priority), \
77+
STEP_PRIORITY(step_index, 5, priority), \
78+
STEP_PRIORITY(step_index, 6, priority), \
79+
STEP_PRIORITY(step_index, 7, priority), \
80+
STEP_PRIORITY(step_index, 8, priority), \
81+
STEP_PRIORITY(step_index, 9, priority), \
82+
STEP_PRIORITY(step_index, 10, priority), \
83+
STEP_PRIORITY(step_index, 11, priority), \
84+
STEP_PRIORITY(step_index, 12, priority), \
85+
STEP_PRIORITY(step_index, 13, priority), \
86+
STEP_PRIORITY(step_index, 14, priority), \
87+
STEP_PRIORITY(step_index, 15, priority), \
88+
STEP_PRIORITY(step_index, 16, priority), \
89+
STEP_PRIORITY(step_index, 17, priority), \
90+
NULL \
91+
}
92+
93+
#define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\
94+
(&(const struct attribute_group){\
95+
.attrs = (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\
96+
.is_visible = tgu_node_visible,\
97+
.name = "step" #step "_priority" #priority \
98+
})
99+
100+
enum operation_index {
101+
TGU_PRIORITY0,
102+
TGU_PRIORITY1,
103+
TGU_PRIORITY2,
104+
TGU_PRIORITY3
105+
106+
};
107+
108+
/* Maximum priority that TGU supports */
109+
#define MAX_PRIORITY 4
110+
111+
struct tgu_attribute {
112+
struct device_attribute attr;
113+
u32 step_index;
114+
enum operation_index operation_index;
115+
u32 reg_num;
116+
};
117+
118+
struct value_table {
119+
unsigned int *priority;
120+
};
121+
16122
/**
17123
* struct tgu_drvdata - Data structure for a TGU (Trigger Generator Unit)
18124
* @base: Memory-mapped base address of the TGU device
19125
* @dev: Pointer to the associated device structure
20126
* @csdev: Pointer to the associated coresight device
21127
* @spinlock: Spinlock for handling concurrent access
22128
* @enable: Flag indicating whether the TGU device is enabled
129+
* @value_table: Store given value based on relevant parameters.
130+
* @max_reg: Maximum number of registers
131+
* @max_step: Maximum step size
23132
*
24133
* This structure defines the data associated with a TGU device,
25134
* including its base address, device pointers, clock, spinlock for
@@ -32,6 +141,9 @@ struct tgu_drvdata {
32141
struct coresight_device *csdev;
33142
spinlock_t spinlock;
34143
bool enable;
144+
struct value_table *value_table;
145+
int max_reg;
146+
int max_step;
35147
};
36148

37149
#endif

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