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Add CAMSS and IMX577 sensor support for Shikra EVK (#668)
Add CAMSS and IMX577 sensor support for Shikra EVK
2 parents cc3a959 + 0f38729 commit f450f88

10 files changed

Lines changed: 355 additions & 1 deletion

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‎Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml‎

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@@ -34,6 +34,7 @@ properties:
3434
- qcom,sc8280xp-cci
3535
- qcom,sdm670-cci
3636
- qcom,sdm845-cci
37+
- qcom,shikra-cci
3738
- qcom,sm6150-cci
3839
- qcom,sm6350-cci
3940
- qcom,sm8250-cci
@@ -136,6 +137,7 @@ allOf:
136137
- qcom,kaanapali-cci
137138
- qcom,qcm2290-cci
138139
- qcom,qcs8300-cci
140+
- qcom,shikra-cci
139141
- qcom,sm8750-cci
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then:
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properties:

‎Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml‎

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@@ -8,13 +8,16 @@ title: Qualcomm QCM2290 Camera Subsystem (CAMSS)
88

99
maintainers:
1010
- Loic Poulain <loic.poulain@oss.qualcomm.com>
11+
- Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
1112

1213
description:
1314
The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
1415

1516
properties:
1617
compatible:
17-
const: qcom,qcm2290-camss
18+
enum:
19+
- qcom,qcm2290-camss
20+
- qcom,shikra-camss
1821

1922
reg:
2023
maxItems: 9
@@ -76,6 +79,7 @@ properties:
7679
- const: sf_mnoc
7780

7881
iommus:
82+
minItems: 1
7983
maxItems: 4
8084

8185
power-domains:

‎arch/arm64/boot/dts/qcom/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -348,6 +348,14 @@ dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb
348348
dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk.dtb
349349
dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk.dtb
350350
dtb-$(CONFIG_ARCH_QCOM) += shikra-iqs-evk.dtb
351+
352+
shikra-cqm-evk-imx577-camera-dtbs := shikra-cqm-evk.dtb shikra-cqm-evk-imx577-camera.dtbo
353+
shikra-cqs-evk-imx577-camera-dtbs := shikra-cqs-evk.dtb shikra-cqm-evk-imx577-camera.dtbo
354+
shikra-iqs-evk-imx577-camera-dtbs := shikra-iqs-evk.dtb shikra-iqs-evk-imx577-camera.dtbo
355+
356+
dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk-imx577-camera.dtb
357+
dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk-imx577-camera.dtb
358+
dtb-$(CONFIG_ARCH_QCOM) += shikra-iqs-evk-imx577-camera.dtb
351359
dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb
352360
dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb
353361
dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb

‎arch/arm64/boot/dts/qcom/shikra-cqm-evk-imx577-camera.dtso‎

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@@ -0,0 +1,63 @@
1+
// SPDX-License-Identifier: BSD-3-Clause
2+
/*
3+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4+
*/
5+
6+
/dts-v1/;
7+
/plugin/;
8+
9+
#include <dt-bindings/clock/qcom,shikra-gcc.h>
10+
#include <dt-bindings/gpio/gpio.h>
11+
12+
&camss {
13+
vdd-csiphy-1p2-supply = <&pm4125_l5>;
14+
vdd-csiphy-1p8-supply = <&pm4125_l13>;
15+
16+
status = "okay";
17+
18+
ports {
19+
#address-cells = <1>;
20+
#size-cells = <0>;
21+
22+
port@1 {
23+
reg = <1>;
24+
25+
csiphy1_ep: endpoint {
26+
data-lanes = <0 1 2 3>;
27+
remote-endpoint = <&imx577_ep1>;
28+
};
29+
};
30+
};
31+
};
32+
33+
&cci {
34+
status = "okay";
35+
};
36+
37+
&cci_i2c1 {
38+
#address-cells = <1>;
39+
#size-cells = <0>;
40+
41+
camera@1a {
42+
compatible = "sony,imx577";
43+
reg = <0x1a>;
44+
45+
reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
46+
pinctrl-0 = <&mclk1_default>;
47+
pinctrl-names = "default";
48+
49+
clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
50+
assigned-clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
51+
assigned-clock-rates = <24000000>;
52+
53+
dovdd-supply = <&pm4125_l15>;
54+
55+
port {
56+
imx577_ep1: endpoint {
57+
link-frequencies = /bits/ 64 <600000000>;
58+
data-lanes = <0 1 2 3>;
59+
remote-endpoint = <&csiphy1_ep>;
60+
};
61+
};
62+
};
63+
};

‎arch/arm64/boot/dts/qcom/shikra-iqs-evk-imx577-camera.dtso‎

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1+
// SPDX-License-Identifier: BSD-3-Clause
2+
/*
3+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4+
*/
5+
6+
/dts-v1/;
7+
/plugin/;
8+
9+
#include <dt-bindings/clock/qcom,shikra-gcc.h>
10+
#include <dt-bindings/gpio/gpio.h>
11+
12+
&camss {
13+
vdd-csiphy-1p2-supply = <&pm8150_l11>;
14+
vdd-csiphy-1p8-supply = <&pm8150_l12>;
15+
16+
status = "okay";
17+
18+
ports {
19+
#address-cells = <1>;
20+
#size-cells = <0>;
21+
22+
port@1 {
23+
reg = <1>;
24+
25+
csiphy1_ep: endpoint {
26+
data-lanes = <0 1 2 3>;
27+
remote-endpoint = <&imx577_ep1>;
28+
};
29+
};
30+
};
31+
};
32+
33+
&cci {
34+
status = "okay";
35+
};
36+
37+
&cci_i2c1 {
38+
#address-cells = <1>;
39+
#size-cells = <0>;
40+
41+
camera@1a {
42+
compatible = "sony,imx577";
43+
reg = <0x1a>;
44+
45+
reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
46+
pinctrl-0 = <&mclk1_default>;
47+
pinctrl-names = "default";
48+
49+
clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
50+
assigned-clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
51+
assigned-clock-rates = <24000000>;
52+
53+
dovdd-supply = <&pm8150_l15>;
54+
55+
port {
56+
imx577_ep1: endpoint {
57+
link-frequencies = /bits/ 64 <600000000>;
58+
data-lanes = <0 1 2 3>;
59+
remote-endpoint = <&csiphy1_ep>;
60+
};
61+
};
62+
};
63+
};

‎arch/arm64/boot/dts/qcom/shikra.dtsi‎

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@@ -516,6 +516,66 @@
516516
gpio-ranges = <&tlmm 0 0 165>;
517517
wakeup-parent = <&mpm>;
518518

519+
cci_i2c0_default: cci-i2c0-default-state {
520+
/* SDA, SCL */
521+
pins = "gpio36", "gpio37";
522+
function = "cci_i2c0";
523+
drive-strength = <2>;
524+
bias-pull-up;
525+
};
526+
527+
cci_i2c0_sleep: cci-i2c0-sleep-state {
528+
/* SDA, SCL */
529+
pins = "gpio36", "gpio37";
530+
function = "cci_i2c0";
531+
drive-strength = <2>;
532+
bias-pull-down;
533+
};
534+
535+
cci_i2c1_default: cci-i2c1-default-state {
536+
/* SDA, SCL */
537+
pins = "gpio41", "gpio42";
538+
function = "cci_i2c1";
539+
drive-strength = <2>;
540+
bias-pull-up;
541+
};
542+
543+
cci_i2c1_sleep: cci-i2c1-sleep-state {
544+
/* SDA, SCL */
545+
pins = "gpio41", "gpio42";
546+
function = "cci_i2c1";
547+
drive-strength = <2>;
548+
bias-pull-down;
549+
};
550+
551+
mclk0_default: mclk0-default-state {
552+
pins = "gpio34";
553+
function = "cam_mclk";
554+
drive-strength = <2>;
555+
bias-disable;
556+
};
557+
558+
mclk1_default: mclk1-default-state {
559+
pins = "gpio35";
560+
function = "cam_mclk";
561+
drive-strength = <2>;
562+
bias-disable;
563+
};
564+
565+
mclk2_default: mclk2-default-state {
566+
pins = "gpio96";
567+
function = "cam_mclk";
568+
drive-strength = <2>;
569+
bias-disable;
570+
};
571+
572+
mclk3_default: mclk3-default-state {
573+
pins = "gpio98";
574+
function = "cam_mclk";
575+
drive-strength = <2>;
576+
bias-disable;
577+
};
578+
519579
qup_i2c0_data_clk: qup-i2c0-data-clk-state {
520580
/* SDA, SCL */
521581
pins = "gpio2", "gpio3";
@@ -1119,6 +1179,142 @@
11191179
};
11201180
};
11211181

1182+
camss: camss@5c11000 {
1183+
compatible = "qcom,shikra-camss";
1184+
1185+
reg = <0x0 0x05c11000 0x0 0x1000>,
1186+
<0x0 0x05c6e000 0x0 0x1000>,
1187+
<0x0 0x05c75000 0x0 0x1000>,
1188+
<0x0 0x05c52000 0x0 0x1000>,
1189+
<0x0 0x05c53000 0x0 0x1000>,
1190+
<0x0 0x05c66000 0x0 0x400>,
1191+
<0x0 0x05c68000 0x0 0x400>,
1192+
<0x0 0x05c6f000 0x0 0x4000>,
1193+
<0x0 0x05c76000 0x0 0x4000>;
1194+
reg-names = "top",
1195+
"csid0",
1196+
"csid1",
1197+
"csiphy0",
1198+
"csiphy1",
1199+
"csitpg0",
1200+
"csitpg1",
1201+
"vfe0",
1202+
"vfe1";
1203+
1204+
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
1205+
<&gcc GCC_CAMSS_AXI_CLK>,
1206+
<&gcc GCC_CAMSS_NRT_AXI_CLK>,
1207+
<&gcc GCC_CAMSS_RT_AXI_CLK>,
1208+
<&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
1209+
<&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
1210+
<&gcc GCC_CAMSS_CPHY_0_CLK>,
1211+
<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1212+
<&gcc GCC_CAMSS_CPHY_1_CLK>,
1213+
<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1214+
<&gcc GCC_CAMSS_TOP_AHB_CLK>,
1215+
<&gcc GCC_CAMSS_TFE_0_CLK>,
1216+
<&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
1217+
<&gcc GCC_CAMSS_TFE_1_CLK>,
1218+
<&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>;
1219+
clock-names = "ahb",
1220+
"axi",
1221+
"camnoc_nrt_axi",
1222+
"camnoc_rt_axi",
1223+
"csi0",
1224+
"csi1",
1225+
"csiphy0",
1226+
"csiphy0_timer",
1227+
"csiphy1",
1228+
"csiphy1_timer",
1229+
"top_ahb",
1230+
"vfe0",
1231+
"vfe0_cphy_rx",
1232+
"vfe1",
1233+
"vfe1_cphy_rx";
1234+
1235+
interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING 0>,
1236+
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING 0>,
1237+
<GIC_SPI 72 IRQ_TYPE_EDGE_RISING 0>,
1238+
<GIC_SPI 73 IRQ_TYPE_EDGE_RISING 0>,
1239+
<GIC_SPI 309 IRQ_TYPE_EDGE_RISING 0>,
1240+
<GIC_SPI 310 IRQ_TYPE_EDGE_RISING 0>,
1241+
<GIC_SPI 211 IRQ_TYPE_EDGE_RISING 0>,
1242+
<GIC_SPI 213 IRQ_TYPE_EDGE_RISING 0>;
1243+
interrupt-names = "csid0",
1244+
"csid1",
1245+
"csiphy0",
1246+
"csiphy1",
1247+
"csitpg0",
1248+
"csitpg1",
1249+
"vfe0",
1250+
"vfe1";
1251+
1252+
interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
1253+
&config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>,
1254+
<&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG
1255+
&mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1256+
<&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG
1257+
&mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1258+
interconnect-names = "ahb",
1259+
"hf_mnoc",
1260+
"sf_mnoc";
1261+
1262+
iommus = <&apps_smmu 0x400 0x0>;
1263+
power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
1264+
1265+
status = "disabled";
1266+
1267+
ports {
1268+
#address-cells = <1>;
1269+
#size-cells = <0>;
1270+
1271+
port@0 {
1272+
reg = <0>;
1273+
};
1274+
1275+
port@1 {
1276+
reg = <1>;
1277+
};
1278+
};
1279+
};
1280+
1281+
cci: cci@5c1b000 {
1282+
compatible = "qcom,shikra-cci", "qcom,msm8996-cci";
1283+
reg = <0x0 0x05c1b000 0x0 0x1000>;
1284+
1285+
interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING 0>;
1286+
1287+
clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1288+
<&gcc GCC_CAMSS_CCI_0_CLK>;
1289+
clock-names = "ahb",
1290+
"cci";
1291+
1292+
power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
1293+
1294+
pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>;
1295+
pinctrl-1 = <&cci_i2c0_sleep &cci_i2c1_sleep>;
1296+
pinctrl-names = "default", "sleep";
1297+
1298+
#address-cells = <1>;
1299+
#size-cells = <0>;
1300+
1301+
status = "disabled";
1302+
1303+
cci_i2c0: i2c-bus@0 {
1304+
reg = <0>;
1305+
clock-frequency = <400000>;
1306+
#address-cells = <1>;
1307+
#size-cells = <0>;
1308+
};
1309+
1310+
cci_i2c1: i2c-bus@1 {
1311+
reg = <1>;
1312+
clock-frequency = <400000>;
1313+
#address-cells = <1>;
1314+
#size-cells = <0>;
1315+
};
1316+
};
1317+
11221318
sdhc_ice: crypto@4748000 {
11231319
compatible = "qcom,shikra-inline-crypto-engine",
11241320
"qcom,inline-crypto-engine";

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