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| 1 | +# THE QUANUX PERFORMANCE MANIFESTO |
| 2 | +**The End of Permission-Based Execution** |
| 3 | + |
| 4 | +## Preamble: The Sovereignty of the Nanosecond |
| 5 | +For decades, institutional trading has been a series of requests for permission. A strategy asks the OS for CPU time. The OS asks the Kernel for a packet. The Kernel asks the NIC for a wire. Each request is a debt paid in latency. |
| 6 | + |
| 7 | +QuanuX is the end of the debt. We have crossed the Rubicon from "Software Applications" to "Hardware-Enforced Logic Gates." We do not ask the Operating System for permission to trade; we have colonized the silicon to make execution a physical inevitability. |
| 8 | + |
| 9 | +### I. The Law of the Dead Core (The Executioner) |
| 10 | +We have rejected the lie of "Multithreading." Threads are a software illusion managed by an entropic scheduler. QuanuX operates via Physical Core Isolation. |
| 11 | + |
| 12 | +The Spreader Core (Core 3) is a "Dead Core." It is isolated from the Linux scheduler. It does not sleep; it does not context-switch. It runs a bare-metal C++ loop that owns the L1 cache. |
| 13 | + |
| 14 | +* **The Metric:** 59 Nanoseconds from Tick-to-Signal. |
| 15 | +* **The Physics:** By pinning logic to the hardware's voltage cycles, we have removed the "Operating System Jitter" from the hot-path. |
| 16 | + |
| 17 | +### II. The Sovereign Sentinel (The L3 Interlock) |
| 18 | +Traditional Risk Management is an if/else statement—a software check that can be bypassed by memory corruption or logic errors. In QuanuX, Risk is a Hardware Gate. |
| 19 | + |
| 20 | +The Sentinel (Core 5) runs on its own isolated silicon. It monitors the "Sins" of the machine (Stale Data, Notional Breach, Order Storms). |
| 21 | + |
| 22 | +* **The Interlock:** If a rule is violated, the Sentinel executes an `asm lock orb` instruction on the L3 Cache Bus. |
| 23 | +* **The Metric:** 11.33 Nanoseconds Time-to-Halt. |
| 24 | +* **The Physics:** The Spreader physically cannot traverse its pipeline if the 0th bit of the L3 Sovereign block is flipped. We have turned the L3 cache into a physical circuit breaker. |
| 25 | + |
| 26 | +### III. The L3 Tap (The Visual Witness) |
| 27 | +To observe a system is to disturb it—unless you observe through the L3 Tap. We have abolished traditional logging. |
| 28 | + |
| 29 | +* **The Tap:** The Execution Core "bleeds" its internal Price DOM and Alpha state into a 64-byte aligned circular buffer in the L3 cache. |
| 30 | +* **The Witness:** Our Rust/Tauri "Clerk" reads this buffer asynchronously. The Spreader never knows it's being watched. |
| 31 | +* **The Physics:** Zero-Jitter Telemetry. We provide a 100% accurate reconstruction of the "Moment of Impact" without adding a single nanosecond to the trade. |
| 32 | + |
| 33 | +### IV. The Remote Neural Interface (The Retina) |
| 34 | +We have decoupled the Human from the Machine to unite them at "Neural Speed." |
| 35 | + |
| 36 | +* **Ref-Buffer Protocol:** The React frontend is a "Dumb Terminal" that paints the market at the monitor's native refresh rate (up to 240Hz) using imperative Canvas rendering. |
| 37 | +* **The Metric:** 120 Microseconds Tick-to-Pixel. |
| 38 | +* **The Physics:** By bypassing the React Virtual DOM diffing engine for telemetry, we deliver market reality to the human retina faster than the human nervous system can process a standard "blink." |
| 39 | + |
| 40 | +### V. Git-as-Governance (The Cryptographic Seal) |
| 41 | +Institutional credibility is built on Binary Integrity. |
| 42 | + |
| 43 | +* **The Seal:** No strategy can be deployed unless its SHA-256 hash matches a Signed Git Commit. |
| 44 | +* **The Physics:** We have replaced "Administrative Permissions" with Mathematical Certainty. The machine only executes what the repository has immortalized. |
| 45 | + |
| 46 | +--- |
| 47 | + |
| 48 | +## Conclusion: Argue with Physics |
| 49 | +If you wish to challenge the dominance of QuanuX, do not bring a code auditor. Bring a physicist. |
| 50 | + |
| 51 | +Our latency is not a "target"; it is a function of the clock-speed of the CPU and the speed of light in the L3 bus. We have moved the battleground from the "Application Layer" to the "Physical Layer." |
| 52 | + |
| 53 | +The Spaceboat is launched. The Sentinel is awake. The 59ns heartbeats are live. |
| 54 | + |
| 55 | +--- |
| 56 | + |
| 57 | +## APPENDIX A: INSTITUTIONAL DUE DILIGENCE & SURVIVABILITY |
| 58 | +*The Binary Standard for Mission-Critical HFT Systems* |
| 59 | + |
| 60 | +This appendix serves as the formal response to the "Institutional 8" requirements. It bridges the gap between the Sovereign Execution Paradox and the requirements of global clearing firms and multi-billion dollar prop groups. |
| 61 | + |
| 62 | +### 1. Deterministic State & Failure Recovery |
| 63 | +**The Objection:** "What happens if the process crashes mid-fill?" |
| 64 | +**The QuanuX Answer:** QuanuX utilizes Persistent Shared Memory (HugePages) for its internal state machine. If the execution kernel (Core 3) is terminated, the state is not lost; it remains "Hot" in the L3 cache and RAM. |
| 65 | +**The Recovery:** A "Warm Restart" takes <50 microseconds. The new process attaches to the existing memory segment, recognizes the `STATE_PARTIAL` flag, and immediately resumes hedging—bypassing the need for a full exchange re-sync in critical moments. |
| 66 | + |
| 67 | +### 2. Hardware-Level Risk Enforcement (The Sentinel) |
| 68 | +**The Objection:** "Can a strategy bug bypass your risk limits?" |
| 69 | +**The QuanuX Answer:** No. Risk is asymmetric and external. The Risk Sentinel (Core 5) and the Spreader (Core 3) occupy different physical silicon. |
| 70 | +**The Logic:** Even if the Spreader's memory is corrupted or it enters an infinite loop, the Sentinel continues to monitor the L3 Tap independently. The 11.33ns Halt is a bus-level event that overrides the Spreader's logic. |
| 71 | + |
| 72 | +### 3. Sim-to-Live Parity (Zero PnL Drift) |
| 73 | +**The Objection:** "How do we know backtests match live results?" |
| 74 | +**The QuanuX Answer:** We utilize a Common Kernel Architecture. The same C++ object code is used for Live and Simulation. |
| 75 | +**The Mechanism:** We use TSC-Injection. In simulation, the engine is "tricked" by a hardware-clock-emulator that feeds it historical packet timestamps. The engine's internal state machine reacts to "simulated time" with the exact same logic gates used in the live environment. |
| 76 | + |
| 77 | +### 4. Governance & Cryptographic Provenance |
| 78 | +**The Objection:** "Who authorized this strategy change?" |
| 79 | +**The QuanuX Answer:** QuanuX implements Git-as-Governance. Every parameter change and logic update is a signed commit. |
| 80 | +**The Enforcement:** The `invoke_hot_swap` command in the Tauri backend performs a SHA-256 verification. If the binary hash does not match a verified, signed commit in the audit log, the L3 Sentinel will refuse to lift the `risk_interlock`, and the system will remain in `STATE_HALT`. |
| 81 | + |
| 82 | +### 5. Latency Budget Transparency |
| 83 | +**The Objection:** "What is the end-to-end wire-to-wire latency?" |
| 84 | +**The QuanuX Answer:** We provide an honest Full-Stack Budget: |
| 85 | + |
| 86 | +* NIC Ingress (Kernel Bypass/Solarflare): ~800ns |
| 87 | +* QuanuX C++ Core Processing: 59ns |
| 88 | +* L3 Risk Interlock Check: 11ns |
| 89 | +* NIC Egress: ~800ns |
| 90 | + |
| 91 | +**Total Internal Budget:** <2 microseconds (Excluding external wire travel). |
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