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A netlist describes all the electrical connection between then components of a Printed Circuit Board. A typical Altium Designer generated Netlist looks like this::
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A netlist describes all the electrical connections between components on a Printed Circuit Board (PCB). This library parses netlists and provides utilities for analyzing connectivity, finding pins, and performing automated checks.
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**Supported formats:**
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- Altium Designer netlists
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- Other similar netlist formats
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Installation
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============
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Install using pip::
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pip install netlist
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Or for development::
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pip install -e .
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**Requirements:** Python 3.8 or higher (tested up to Python 3.16)
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Quick Start
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===========
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Basic usage::
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from python_netlist import Netlist
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# Parse a netlist file
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nl = Netlist('my_board.net')
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# Check for orphaned nets (nets with <2 connections)
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orphans = nl.check_orphans()
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# Find pins on a specific net
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pins = nl.find_pins('VCC', connector_map)
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Features
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========
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**Net Parsing**
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Parse netlist files to extract component connections and signal information.
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**Pin Finding**
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Map net names to physical connector pins using connector definitions.
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**Automated Checks**
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Detect common schematic errors like unconnected pins and orphaned nets.
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**Command-line Interface**
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Analyze netlists directly from the terminal.
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Netlist Format
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==============
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A typical Altium Designer generated netlist looks like this::
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Wire List
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@@ -31,58 +89,85 @@ A netlist describes all the electrical connection between then components of a P
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It contains
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1. a very crude BOM (value, designator, package)
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2. A list of all signal names and their connection.
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The netlist contains:
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In this example, 2 components are defined, and 2 nets are defined.
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1. A basic BOM (value, designator, package)
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2. A list of all signal names and their connections
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This module ignores the BOM, and concentrates only on nets.
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**Note:** This module focuses on net connectivity and ignores the BOM section.
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SOM connection helper
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SOM Connection Helper
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=====================
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On large System On Module, it can be very tedious and error-prone to define the different signal connection in device trees, or in an Hardware Design (for FPGA designs)
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For large System On Module (SOM) designs, it can be tedious and error-prone to manually define signal connections in device trees or FPGA hardware designs.
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Using the ``find_pins`` function, you can retrieve pin names based on net names.
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**Connector Definition Example**
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Using to the `find_pins` function, it is possible to retreive pin names from on a net name.
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You first have to define your module connectors and pins this way::
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Define your module connectors and pins::
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pz_pins = {
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"JX1": {
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"9": "R19",
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"10": "T19",
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"11": "T11",
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"12": "T12",
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"13": "T10",
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"14": "U12",
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"JX1": {
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"9": "R19",
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"10": "T19",
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"11": "T11",
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"12": "T12",
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"13": "T10",
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"14": "U12",
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},
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"JX2": {
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"13": "G14",
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"14": "J15",
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"17": "C20",
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"18": "B19",
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"JX2": {
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"13": "G14",
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"14": "J15",
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"17": "C20",
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"18": "B19",
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},
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}
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in this example, the SOM has 2 connectors which are seperate parts on the PCB, called "JX1" and "JX2". Pin 9 of connector JX1 is named pin "R19" internally in the SOM.
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In this example:
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- The SOM has 2 connector parts: ``JX1`` and ``JX2``
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- Pin 9 of connector ``JX1`` maps to internal pin ``R19``
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This also works on components which have a single part (in this example only the first 2 pins are described)::
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**Single-Part Component Example**
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stmf32F407_64_pins = {
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"1" : "VBAT",
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"2" : "PC13",
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Works for components with a single part (showing first 2 pins)::
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stm32f407_64_pins = {
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"1": "VBAT",
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"2": "PC13",
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}
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Automatic Checks
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================
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Common Schematic capture mistakes can be caught analyzing the Netlist. The most common is probably unconnected pins due to a bad net label.
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Catch common schematic capture mistakes by analyzing the netlist.
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**Orphan Detection**
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`check_orphans`lists all nets that have (by default) less than 2 connections.
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The ``check_orphans`` function lists all nets with fewer than 2 connections (configurable), which often indicates connection errors::
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