drm: Force write-combined mappings for DMA

PCIe GPU device drivers may use normal cached mappings for DMA memory.

This requires the PCIe interface to be coherent with the CPU caches,
which is not supported by many Arm platforms (e.g. RK35xx), leading to
data corruption on inbound transactions.

Add an option to force write-combined mappings instead (Normal
non-cacheable on Arm).

Note that this is just a band-aid to keep the patch small. The TTM
allocator should frankly not be concerned with hardware limitations and
always pass the requested caching type (a driver could still use cached
memory and perform its own cache maintenance).

A proper solution would be for GPU drivers to check whether the device
supports coherency and request the appropriate caching type. The
drm_arch_can_wc_memory() helper also needs to be reworked or possibly
even dropped.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

Author: mariobalanica

drivers/gpu/drm/Kconfig

@@ -183,6 +183,22 @@ config DRM_LOAD_EDID_FIRMWARE
 	  default case is N. Details and instructions how to build your own
 	  EDID data are given in Documentation/admin-guide/edid.rst.
 
+config DRM_FORCE_DMA_WRITE_COMBINED_MAPPINGS
+	bool "Force write-combined mappings for DMA"
+	default y
+	help
+	  PCIe GPU device drivers may use normal cached mappings for DMA memory.
+
+	  This requires the PCIe interface to be coherent with the CPU caches,
+	  which is not supported by many Arm platforms (e.g. RK35xx), leading to
+	  data corruption on inbound transactions.
+
+	  Enable this option to force write-combined mappings instead (Normal
+	  non-cacheable on Arm).
+
+	  Disable if the hardware supports coherency, as it might cause issues on
+	  certain platforms that ignore the PCIe NoSnoop TLP attribute.
+
 source "drivers/gpu/drm/display/Kconfig"
 
 config DRM_TTM

drivers/gpu/drm/ttm/ttm_tt.c

@@ -154,6 +154,10 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm,
 			       enum ttm_caching caching,
 			       unsigned long extra_pages)
 {
+#ifdef CONFIG_DRM_FORCE_DMA_WRITE_COMBINED_MAPPINGS
+	if (caching == ttm_cached)
+		caching = ttm_write_combined;
+#endif
 	ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) + extra_pages;
 	ttm->page_flags = page_flags;
 	ttm->dma_address = NULL;

include/drm/drm_cache.h

@@ -45,6 +45,9 @@ bool drm_need_swiotlb(int dma_bits);
 
 static inline bool drm_arch_can_wc_memory(void)
 {
+#ifdef CONFIG_DRM_FORCE_DMA_WRITE_COMBINED_MAPPINGS
+	return true;
+#endif
 #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
 	return false;
 #elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON64)