@@ -744,6 +744,11 @@ v3d_gpu_reset_for_timeout(struct v3d_dev *v3d, struct drm_sched_job *sched_job)
744744 return DRM_GPU_SCHED_STAT_NOMINAL ;
745745}
746746
747+ /* If the current address or return address have changed, then the GPU
748+ * has probably made progress and we should delay the reset. This
749+ * could fail if the GPU got in an infinite loop in the CL, but that
750+ * is pretty unlikely outside of an i-g-t testcase.
751+ */
747752static enum drm_gpu_sched_stat
748753v3d_cl_job_timedout (struct drm_sched_job * sched_job , enum v3d_queue q ,
749754 u32 * timedout_ctca , u32 * timedout_ctra )
@@ -753,16 +758,9 @@ v3d_cl_job_timedout(struct drm_sched_job *sched_job, enum v3d_queue q,
753758 u32 ctca = V3D_CORE_READ (0 , V3D_CLE_CTNCA (q ));
754759 u32 ctra = V3D_CORE_READ (0 , V3D_CLE_CTNRA (q ));
755760
756- /* If the current address or return address have changed, then the GPU
757- * has probably made progress and we should delay the reset. This
758- * could fail if the GPU got in an infinite loop in the CL, but that
759- * is pretty unlikely outside of an i-g-t testcase.
760- */
761761 if (* timedout_ctca != ctca || * timedout_ctra != ctra ) {
762762 * timedout_ctca = ctca ;
763763 * timedout_ctra = ctra ;
764-
765- list_add (& sched_job -> list , & sched_job -> sched -> pending_list );
766764 return DRM_GPU_SCHED_STAT_NOMINAL ;
767765 }
768766
@@ -802,13 +800,11 @@ v3d_csd_job_timedout(struct drm_sched_job *sched_job)
802800 struct v3d_dev * v3d = job -> base .v3d ;
803801 u32 batches = V3D_CORE_READ (0 , V3D_CSD_CURRENT_CFG4 (v3d -> ver ));
804802
805- /* If we've made progress, skip reset, add the job to the pending
806- * list, and let the timer get rearmed.
803+ /* If we've made progress, skip reset and let the timer get
804+ * rearmed.
807805 */
808806 if (job -> timedout_batches != batches ) {
809807 job -> timedout_batches = batches ;
810-
811- list_add (& sched_job -> list , & sched_job -> sched -> pending_list );
812808 return DRM_GPU_SCHED_STAT_NOMINAL ;
813809 }
814810
0 commit comments