@@ -1336,11 +1336,11 @@ static void dwc3_set_axi_pipe_limit(struct dwc3 *dwc)
13361336 dev_err (dev , "Invalid axi_pipe_limit property\n" );
13371337 return ;
13381338 }
1339- cfg = dwc3_readl (dwc -> regs , DWC3_GSBUSCFG1 );
1339+ cfg = dwc3_readl (dwc , DWC3_GSBUSCFG1 );
13401340 cfg &= ~DWC3_GSBUSCFG1_PIPETRANSLIMIT (15 );
13411341 cfg |= DWC3_GSBUSCFG1_PIPETRANSLIMIT (dwc -> axi_pipe_limit - 1 );
13421342
1343- dwc3_writel (dwc -> regs , DWC3_GSBUSCFG1 , cfg );
1343+ dwc3_writel (dwc , DWC3_GSBUSCFG1 , cfg );
13441344}
13451345
13461346/**
@@ -1554,7 +1554,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
15541554 u8 tx_maxburst = dwc -> tx_max_burst_prd ;
15551555
15561556 if (tx_thr_num && tx_maxburst ) {
1557- reg = dwc3_readl (dwc -> regs , DWC3_GTXTHRCFG );
1557+ reg = dwc3_readl (dwc , DWC3_GTXTHRCFG );
15581558 reg |= DWC3_GTXTHRCFG_PKTCNTSEL ;
15591559
15601560 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT (~0 );
@@ -1563,7 +1563,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
15631563 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE (~0 );
15641564 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE (tx_maxburst );
15651565
1566- dwc3_writel (dwc -> regs , DWC3_GTXTHRCFG , reg );
1566+ dwc3_writel (dwc , DWC3_GTXTHRCFG , reg );
15671567 }
15681568 }
15691569
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