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lines changed Original file line number Diff line number Diff line change @@ -1262,6 +1262,8 @@ static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
12621262static int bcm2835_clock_determine_rate (struct clk_hw * hw ,
12631263 struct clk_rate_request * req )
12641264{
1265+ struct bcm2835_clock * clock = bcm2835_clock_from_hw (hw );
1266+ struct bcm2835_cprman * cprman = clock -> cprman ;
12651267 struct clk_hw * parent , * best_parent = NULL ;
12661268 bool current_parent_is_pllc ;
12671269 unsigned long rate , best_rate = 0 ;
@@ -1281,13 +1283,17 @@ static int bcm2835_clock_determine_rate(struct clk_hw *hw,
12811283 continue ;
12821284
12831285 /*
1286+ * BCM2835 only.
12841287 * Don't choose a PLLC-derived clock as our parent
12851288 * unless it had been manually set that way. PLLC's
12861289 * frequency gets adjusted by the firmware due to
12871290 * over-temp or under-voltage conditions, without
12881291 * prior notification to our clock consumer.
1292+ * (BCM2711 doesn't do this, therefore it is safe to
1293+ * use PLLC)
12891294 */
1290- if (bcm2835_clk_is_pllc (parent ) && !current_parent_is_pllc )
1295+ if ((cprman -> soc & SOC_BCM2835 ) && bcm2835_clk_is_pllc (parent ) &&
1296+ !current_parent_is_pllc )
12911297 continue ;
12921298
12931299 rate = bcm2835_clock_choose_div_and_prate (hw , i , req -> rate ,
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