Add some PIO pseudocode comments; fix up EQ width rounding. TO SQUASH.

Author: njhollinghurst

drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_pio.c

@@ -364,30 +364,30 @@ static int rp1dpi_pio_csync_ilace(struct rp1_dpi *dpi,
 	unsigned short instructions[] = {  /* This is mutable */
 		0x90a0, //  0: pull   block        side 1
 		0x7040, //  1: out    y, 32        side 1
-		//     .wrap_target
-		0x3083, //  2: wait   1 gpio, 3    side 1
-		0xa422, //  3: mov    x, y         side 0 [4]
-		0x2003, //  4: wait   0 gpio, 3    side 0
-		0x12c2, //  5: jmp    pin, 2       side 1 [2]
-		0x3083, //  6: wait   1 gpio, 3    side 1
-		0xc442, //  7: irq    clear 2      side 0 [4]
-		0x2003, //  8: wait   0 gpio, 3    side 0
-		0x30c2, //  9: wait   1 irq, 2     side 1
-		0x10d4, // 10: jmp    pin, 20      side 1
-		0x3083, // 11: wait   1 gpio, 3    side 1
-		0xa442, // 12: nop                 side 0 [4]
-		0x2003, // 13: wait   0 gpio, 3    side 0
-		0xd042, // 14: irq    clear 2      side 1
-		0xd043, // 15: irq    clear 3      side 1
-		0x30c2, // 16: wait   1 irq, 2     side 1
-		0x20c3, // 17: wait   1 irq, 3     side 0
-		0x1054, // 18: jmp    x--, 20      side 1
-		0x1002, // 19: jmp    2            side 1
-		0xd041, // 20: irq    clear 1      side 1
-		0x3083, // 21: wait   1 gpio, 3    side 1
-		0x20c1, // 22: wait   1 irq, 1     side 0
-		0x104e, // 23: jmp    x--, 14      side 1
-		//     .wrap
+		//     .wrap_target                           ; while (true) {
+		0x3083, //  2: wait   1 gpio, 3    side 1     ;   do { @HSync
+		0xa422, //  3: mov    x, y         side 0 [4] ;   CSYNC: x = VSW - 1
+		0x2003, //  4: wait   0 gpio, 3    side 0     ;   CSYNC: HSync->CSync
+		0x12c2, //  5: jmp    pin, 2       side 1 [2] ;   } while (VSync)
+		0x3083, //  6: wait   1 gpio, 3    side 1     ;   @HSync
+		0xc442, //  7: irq    clear 2      side 0 [4] ;   CSYNC: flush IRQ
+		0x2003, //  8: wait   0 gpio, 3    side 0     ;   CSYNC: Hsync->CSync
+		0x30c2, //  9: wait   1 irq, 2     side 1     ;   @midline
+		0x10d4, // 10: jmp    pin, 20      side 1     ;   if (!VSync) goto sync_left;
+		0x3083, // 11: wait   1 gpio, 3    side 1     ;   @HSync
+		0xa442, // 12: nop                 side 0 [4] ;   CSYNC: delay
+		0x2003, // 13: wait   0 gpio, 3    side 0     ;   CSYNC: Hsync->CSync
+		0xd042, // 14: irq    clear 2      side 1     ;   do { flush IRQ
+		0xd043, // 15: irq    clear 3      side 1     ;     flush IRQ
+		0x30c2, // 16: wait   1 irq, 2     side 1     ;     @midline
+		0x20c3, // 17: wait   1 irq, 3     side 0     ;     CSYNC: @BroadRight
+		0x1054, // 18: jmp    x--, 20      side 1     ;     if (x-- == 0)
+		0x1002, // 19: jmp    2            side 1     ;       break;
+		0xd041, // 20: irq    clear 1      side 1     ; sync_left: flush IRQ
+		0x3083, // 21: wait   1 gpio, 3    side 1     ;     @HSync
+		0x20c1, // 22: wait   1 irq, 1     side 0     ;     CSYNC: @BroadLeft
+		0x104e, // 23: jmp    x--, 14      side 1     ;   } while (x--);
+		//     .wrap                                  ; }
 	};
 	struct pio_program prog = {
 		.instructions = instructions,
@@ -519,7 +519,7 @@ static int rp1dpi_pio_csync_tv(struct rp1_dpi *dpi,
 	/* Load parameters (Vsync pattern; EQ pulse width) into ISR and Y */
 	i = (mode->vsync_end - mode->vsync_start <= 5);
 	pio_sm_put(dpi->pio, 0, i ? 0x02ABFFAA : 0xAABFFEAA);
-	pio_sm_put(dpi->pio, 0, clock_get_hz(clk_sys) / (i ? 425532 : 434782));
+	pio_sm_put(dpi->pio, 0, clock_get_hz(clk_sys) / (i ? 425531 : 434782) - 3);
 	pio_sm_exec(dpi->pio, 0, pio_encode_pull(false, false));
 	pio_sm_exec(dpi->pio, 0, pio_encode_out(pio_y, 32));
 	pio_sm_exec(dpi->pio, 0, pio_encode_in(pio_y, 32));