@@ -761,18 +761,11 @@ static void macb_mac_link_up(struct phylink_config *config,
761761 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
762762 * cleared the pipeline and control registers.
763763 */
764-
765- for (q = 0 , queue = bp -> queues ; q < bp -> num_queues ; ++ q , ++ queue )
766- atomic_set (& queue -> full_refill , -1 );
767-
768- bp -> macbgem_ops .mog_init_rings (bp );
769764 macb_init_buffers (bp );
770765
771- for (q = 0 , queue = bp -> queues ; q < bp -> num_queues ; ++ q , ++ queue ) {
772- atomic_set (& queue -> full_refill , bp -> rx_ring_size );
766+ for (q = 0 , queue = bp -> queues ; q < bp -> num_queues ; ++ q , ++ queue )
773767 queue_writel (queue , IER ,
774768 bp -> rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT (HRESP ));
775- }
776769 }
777770
778771 macb_or_gem_writel (bp , NCFGR , ctrl );
@@ -1322,9 +1315,8 @@ static void gem_rx_refill(struct macb_queue *queue)
13221315 struct macb * bp = queue -> bp ;
13231316 struct macb_dma_desc * desc ;
13241317
1325- while (atomic_dec_if_positive (& queue -> full_refill ) >= 0 ||
1326- ((CIRC_SPACE (queue -> rx_prepared_head , queue -> rx_tail , bp -> rx_ring_size ) > 0 ) &&
1327- (atomic_read (& queue -> full_refill ) != -1 ))) {
1318+ while (CIRC_SPACE (queue -> rx_prepared_head , queue -> rx_tail ,
1319+ bp -> rx_ring_size ) > 0 ) {
13281320 entry = macb_rx_ring_wrap (bp , queue -> rx_prepared_head );
13291321
13301322 /* Make hw descriptor updates visible to CPU */
@@ -1449,7 +1441,6 @@ static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
14491441 queue -> stats .rx_dropped ++ ;
14501442 break ;
14511443 }
1452-
14531444 /* now everything is ready for receiving packet */
14541445 queue -> rx_skbuff [entry ] = NULL ;
14551446 len = ctrl & bp -> rx_frm_len_mask ;
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