@@ -42,6 +42,8 @@ v3d_overflow_mem_work(struct work_struct *work)
4242 container_of (work , struct v3d_dev , overflow_mem_work );
4343 struct drm_device * dev = & v3d -> drm ;
4444 struct v3d_bo * bo = v3d_bo_create (dev , NULL /* XXX: GMP */ , 256 * 1024 );
45+ struct v3d_queue_state * queue = & v3d -> queue [V3D_BIN ];
46+ struct v3d_bin_job * bin_job ;
4547 struct drm_gem_object * obj ;
4648 unsigned long irqflags ;
4749
@@ -61,13 +63,15 @@ v3d_overflow_mem_work(struct work_struct *work)
6163 * some binner pool anyway.
6264 */
6365 spin_lock_irqsave (& v3d -> job_lock , irqflags );
64- if (!v3d -> bin_job ) {
66+ bin_job = (struct v3d_bin_job * )queue -> active_job ;
67+
68+ if (!bin_job ) {
6569 spin_unlock_irqrestore (& v3d -> job_lock , irqflags );
6670 goto out ;
6771 }
6872
6973 drm_gem_object_get (obj );
70- list_add_tail (& bo -> unref_head , & v3d -> bin_job -> render -> unref_list );
74+ list_add_tail (& bo -> unref_head , & bin_job -> render -> unref_list );
7175 spin_unlock_irqrestore (& v3d -> job_lock , irqflags );
7276
7377 v3d_mmu_flush_all (v3d );
@@ -79,6 +83,20 @@ v3d_overflow_mem_work(struct work_struct *work)
7983 drm_gem_object_put (obj );
8084}
8185
86+ static void
87+ v3d_irq_signal_fence (struct v3d_dev * v3d , enum v3d_queue q ,
88+ void (* trace_irq )(struct drm_device * , uint64_t ))
89+ {
90+ struct v3d_queue_state * queue = & v3d -> queue [q ];
91+ struct v3d_fence * fence = to_v3d_fence (queue -> active_job -> irq_fence );
92+
93+ v3d_job_update_stats (queue -> active_job , q );
94+ trace_irq (& v3d -> drm , fence -> seqno );
95+
96+ queue -> active_job = NULL ;
97+ dma_fence_signal (& fence -> base );
98+ }
99+
82100static irqreturn_t
83101v3d_irq (int irq , void * arg )
84102{
@@ -102,41 +120,17 @@ v3d_irq(int irq, void *arg)
102120 }
103121
104122 if (intsts & V3D_INT_FLDONE ) {
105- struct v3d_fence * fence =
106- to_v3d_fence (v3d -> bin_job -> base .irq_fence );
107-
108- v3d_job_update_stats (& v3d -> bin_job -> base , V3D_BIN );
109- trace_v3d_bcl_irq (& v3d -> drm , fence -> seqno );
110-
111- v3d -> bin_job = NULL ;
112- dma_fence_signal (& fence -> base );
113-
123+ v3d_irq_signal_fence (v3d , V3D_BIN , trace_v3d_bcl_irq );
114124 status = IRQ_HANDLED ;
115125 }
116126
117127 if (intsts & V3D_INT_FRDONE ) {
118- struct v3d_fence * fence =
119- to_v3d_fence (v3d -> render_job -> base .irq_fence );
120-
121- v3d_job_update_stats (& v3d -> render_job -> base , V3D_RENDER );
122- trace_v3d_rcl_irq (& v3d -> drm , fence -> seqno );
123-
124- v3d -> render_job = NULL ;
125- dma_fence_signal (& fence -> base );
126-
128+ v3d_irq_signal_fence (v3d , V3D_RENDER , trace_v3d_rcl_irq );
127129 status = IRQ_HANDLED ;
128130 }
129131
130132 if (intsts & V3D_INT_CSDDONE (v3d -> ver )) {
131- struct v3d_fence * fence =
132- to_v3d_fence (v3d -> csd_job -> base .irq_fence );
133-
134- v3d_job_update_stats (& v3d -> csd_job -> base , V3D_CSD );
135- trace_v3d_csd_irq (& v3d -> drm , fence -> seqno );
136-
137- v3d -> csd_job = NULL ;
138- dma_fence_signal (& fence -> base );
139-
133+ v3d_irq_signal_fence (v3d , V3D_CSD , trace_v3d_csd_irq );
140134 status = IRQ_HANDLED ;
141135 }
142136
@@ -168,15 +162,7 @@ v3d_hub_irq(int irq, void *arg)
168162 V3D_WRITE (V3D_HUB_INT_CLR , intsts );
169163
170164 if (intsts & V3D_HUB_INT_TFUC ) {
171- struct v3d_fence * fence =
172- to_v3d_fence (v3d -> tfu_job -> base .irq_fence );
173-
174- v3d_job_update_stats (& v3d -> tfu_job -> base , V3D_TFU );
175- trace_v3d_tfu_irq (& v3d -> drm , fence -> seqno );
176-
177- v3d -> tfu_job = NULL ;
178- dma_fence_signal (& fence -> base );
179-
165+ v3d_irq_signal_fence (v3d , V3D_TFU , trace_v3d_tfu_irq );
180166 status = IRQ_HANDLED ;
181167 }
182168
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