diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README
index 60f402cd70f538..9949861b5bf7e7 100644
--- a/arch/arm/boot/dts/overlays/README
+++ b/arch/arm/boot/dts/overlays/README
@@ -5682,14 +5682,22 @@ Name:   vc4-kms-dsi-waveshare-panel-v2
 Info:   Enable the Waveshare DSI-TOUCH series screen
         Requires vc4-kms-v3d to be loaded.
 Load:   dtoverlay=vc4-kms-dsi-waveshare-panel-v2,<param>
-Params: 5_0_inch_a              5.0" 720x1280 2lane
+Params: 3_4_inch_c              3.4" 800x800 2lane
+        4_0_inch_c              4.0" 720x720 2lane
+        5_0_inch_a              5.0" 720x1280 2lane
         5_5_inch_a              5.5" 720x1280 2lane
         7_0_inch_a              7.0" A 720x1280 2lane
         7_0_inch_b              7.0" B 720x1280 2lane
         8_0_inch_a              8.0" 800x1280 2lane
         8_0_inch_a_4lane        8.0" 800x1280 4lane
+        8_8_inch_a              8.8" 480x1920 2lane
+        9_0_inch_b              9.0" 720x1280 2lane
+        9_0_inch_b_4lane        9.0" 720x1280 4lane
         10_1_inch_a             10.1" 800x1280 2lane
         10_1_inch_a_4lane       10.1" 800x1280 4lane
+        10_1_inch_b             10.1" 720x1280 2lane
+        10_1_inch_b_4lane       10.1" 720x1280 4lane
+        12_3_inch_a_4lane       12.3" 720x1920 4lane
         disable_touch           Disable the touch controller
         invx                    Touchscreen inverted x axis
         invy                    Touchscreen inverted y axis
diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dsi-waveshare-panel-v2-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-dsi-waveshare-panel-v2-overlay.dts
index dd983ab59eeb51..ae4e2be264a93d 100644
--- a/arch/arm/boot/dts/overlays/vc4-kms-dsi-waveshare-panel-v2-overlay.dts
+++ b/arch/arm/boot/dts/overlays/vc4-kms-dsi-waveshare-panel-v2-overlay.dts
@@ -50,6 +50,8 @@
 				reg = <0>;
 				compatible = "waveshare,10.1-dsi-touch-a";
 				reset-gpio = <&display_mcu 1 GPIO_ACTIVE_HIGH>;
+				iovcc-gpio = <&display_mcu 4 GPIO_ACTIVE_HIGH>;
+				avdd-gpio = <&display_mcu 0 GPIO_ACTIVE_HIGH>;
 				backlight = <&display_mcu>;
 
 				port {
@@ -76,14 +78,28 @@
 	};
 
 	__overrides__ {
+		3_4_inch_c = <&dsi_panel>, "compatible=waveshare,3.4-dsi-touch-c";
+		4_0_inch_c = <&dsi_panel>, "compatible=waveshare,4.0-dsi-touch-c";
 		5_0_inch_a = <&dsi_panel>, "compatible=waveshare,5.0-dsi-touch-a";
 		5_5_inch_a = <&dsi_panel>, "compatible=waveshare,5.5-dsi-touch-a";
 		7_0_inch_a = <&dsi_panel>, "compatible=waveshare,7.0-dsi-touch-a";
 		7_0_inch_b = <&dsi_panel>, "compatible=waveshare,7.0-dsi-touch-b";
 		8_0_inch_a = <&dsi_panel>, "compatible=waveshare,8.0-dsi-touch-a";
 		8_0_inch_a_4lane = <&dsi_panel>, "compatible=waveshare,8.0-dsi-touch-a-4lane";
+		8_8_inch_a = <&dsi_panel>, "compatible=waveshare,8.8-dsi-touch-a";
+		9_0_inch_b = <&dsi_panel>, "compatible=waveshare,9.0-dsi-touch-b",
+			     <&touch>, "touchscreen-inverted-x";
+		9_0_inch_b_4lane = <&dsi_panel>, "compatible=waveshare,9.0-dsi-touch-b,4lane",
+				   <&touch>, "touchscreen-inverted-x";
 		10_1_inch_a = <&dsi_panel>, "compatible=waveshare,10.1-dsi-touch-a";
 		10_1_inch_a_4lane = <&dsi_panel>, "compatible=waveshare,10.1-dsi-touch-a-4lane";
+		10_1_inch_b = <&dsi_panel>, "compatible=waveshare,10.1-dsi-touch-b",
+			      <&touch>, "touchscreen-inverted-y";
+		10_1_inch_b_4lane = <&dsi_panel>, "compatible=waveshare,10.1-dsi-touch-b,4lane",
+				    <&touch>, "touchscreen-inverted-y";
+		12_3_inch_a_4lane = <&dsi_panel>, "compatible=waveshare,12.3-dsi-touch-a,4lane",
+				    <&touch>, "touchscreen-swapped-x-y",
+				    <&touch>, "touchscreen-inverted-y";
 		disable_touch = <&touch>, "status=disabled";
 		invx = <&touch>,"touchscreen-inverted-x?";
 		invy = <&touch>,"touchscreen-inverted-y?";
diff --git a/drivers/gpu/drm/panel/panel-waveshare-dsi-v2.c b/drivers/gpu/drm/panel/panel-waveshare-dsi-v2.c
index dea949752f891c..cfff92ead5e6e5 100644
--- a/drivers/gpu/drm/panel/panel-waveshare-dsi-v2.c
+++ b/drivers/gpu/drm/panel/panel-waveshare-dsi-v2.c
@@ -37,6 +37,8 @@ struct ws_panel {
 
 	struct regulator *power;
 	struct gpio_desc *reset;
+	struct gpio_desc *iovcc;
+	struct gpio_desc *avdd;
 
 	enum drm_panel_orientation orientation;
 };
@@ -70,6 +72,85 @@ struct panel_init_cmd {
 		}                                                          \
 	}
 
+static const struct panel_init_cmd ws_panel_12_3_a_4lane_init[] = {
+	_INIT_DCS_CMD(0xB9, 0x83, 0x10, 0x2E),
+	_INIT_DCS_CMD(0xE9, 0xCD),
+	_INIT_DCS_CMD(0xBB, 0x01),
+	_INIT_DCS_CMD(0xE9, 0x00),
+	_INIT_DCS_CMD(0xD1, 0x67, 0x2C, 0xFF, 0x05),
+	_INIT_DCS_CMD(0xBE, 0x11, 0x96, 0x89),
+	_INIT_DCS_CMD(0xD9, 0x04, 0x03, 0x04),
+	_INIT_DCS_CMD(0xB1, 0x10, 0xFA, 0xAF, 0xAF, 0x33, 0x33, 0xB1, 0x4D,
+		      0x2F, 0x36, 0x36, 0x36, 0x36, 0x22, 0x21, 0x15, 0x00),
+	_INIT_DCS_CMD(0xB2, 0x00, 0xD0, 0x27, 0x80, 0x00, 0x14, 0x40, 0x2C,
+		      0x32, 0x02, 0x00, 0x00, 0x15, 0x20, 0xD7, 0x00),
+	_INIT_DCS_CMD(0xB4, 0x98, 0xA0, 0x01, 0x01, 0x98, 0xA0, 0x68, 0x50,
+		      0x01, 0xC7, 0x01, 0x58, 0x00, 0xFF, 0x00, 0xFF),
+	_INIT_DCS_CMD(0xB6, 0x4D, 0x4D, 0xE3),
+	_INIT_DCS_CMD(0xBF, 0xFC, 0x85, 0x80),
+	_INIT_DCS_CMD(0xD2, 0x33, 0x33),
+	_INIT_DCS_CMD(0xD3, 0x00, 0x00, 0x00, 0x00, 0x64, 0x04, 0x00, 0x08,
+		      0x08, 0x27, 0x27, 0x22, 0x2F, 0x15, 0x15, 0x04, 0x04,
+		      0x32, 0x10, 0x13, 0x00, 0x13, 0x32, 0x10, 0x1F, 0x00,
+		      0x02, 0x32, 0x17, 0xFD, 0x00, 0x10, 0x00, 0x00, 0x20,
+		      0x30, 0x01, 0x55, 0x21, 0x38, 0x01, 0x55, 0x0F),
+	_INIT_DCS_CMD(0xE0, 0x00, 0x0C, 0x1A, 0x23, 0x2B, 0x4F, 0x64, 0x69,
+		      0x6C, 0x64, 0x77, 0x77, 0x76, 0x80, 0x79, 0x7E, 0x85,
+		      0x9A, 0x97, 0x4D, 0x56, 0x64, 0x70, 0x00, 0x0C, 0x1A,
+		      0x23, 0x2B, 0x4F, 0x64, 0x69, 0x6C, 0x64, 0x77, 0x77,
+		      0x76, 0x80, 0x79, 0x7E, 0x85, 0x9A, 0x97, 0x4D, 0x56,
+		      0x64, 0x76),
+	_INIT_DCS_CMD(0xBD, 0x01),
+	_INIT_DCS_CMD(0xB1, 0x01, 0x9B, 0x01, 0x31),
+	_INIT_DCS_CMD(0xCB, 0x80, 0x36, 0x12, 0x16, 0xC0, 0x28, 0x40, 0x84,
+		      0x22),
+	_INIT_DCS_CMD(0xD3, 0x01, 0x00, 0xFC, 0x00, 0x00, 0x11, 0x10, 0x00,
+		      0x0E, 0x00, 0x01),
+	_INIT_DCS_CMD(0xBD, 0x02),
+	_INIT_DCS_CMD(0xB4, 0x4E, 0x00, 0x33, 0x11, 0x33, 0x88),
+	_INIT_DCS_CMD(0xBF, 0xF2, 0x00, 0x02),
+	_INIT_DCS_CMD(0xBD, 0x00),
+	_INIT_DCS_CMD(0xC0, 0x23, 0x23, 0x22, 0x11, 0xA2, 0x17, 0x00, 0x80,
+		      0x00, 0x00, 0x08, 0x00, 0x63, 0x63),
+	_INIT_DCS_CMD(0xC6, 0xF9),
+	_INIT_DCS_CMD(0xC7, 0x30),
+	_INIT_DCS_CMD(0xC8, 0x00, 0x04, 0x04, 0x00, 0x00, 0x82, 0x13, 0x01),
+	_INIT_DCS_CMD(0xD0, 0x07, 0x04, 0x05),
+	_INIT_DCS_CMD(0xD5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20,
+		      0x21, 0x20, 0x01, 0x00, 0x03, 0x02, 0x05, 0x04, 0x07,
+		      0x06, 0x1A, 0x1A, 0x1A, 0x1A, 0x9A, 0x9A, 0x9A, 0x9A,
+		      0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x21, 0x20, 0x18,
+		      0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18),
+	_INIT_DCS_CMD(0xD6, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21,
+		      0x20, 0x21, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
+		      0x07, 0x1A, 0x1A, 0x1A, 0x1A, 0x1A, 0x1A, 0x1A, 0x1A,
+		      0x18, 0x18, 0x18, 0x18, 0x20, 0x21, 0x20, 0x21, 0x98,
+		      0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98),
+	_INIT_DCS_CMD(0xBD, 0x01),
+	_INIT_DCS_CMD(0xE7, 0x00, 0x34, 0x01, 0x88, 0x0E, 0xBE, 0x0F),
+	_INIT_DCS_CMD(0xBD, 0x00),
+	_INIT_DCS_CMD(0xC2, 0x43, 0xFF, 0x10),
+	_INIT_DCS_CMD(0xCC, 0x02),
+	_INIT_DCS_CMD(0xBD, 0x03),
+	_INIT_DCS_CMD(0xB2, 0x80),
+	_INIT_DCS_CMD(0xBD, 0x00),
+	_INIT_DCS_CMD(0xD8, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
+		      0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0x80, 0x2A, 0xAA, 0xAA,
+		      0xAA, 0xAA, 0x80, 0x2A, 0xAA, 0xAA, 0xAA),
+	_INIT_DCS_CMD(0xBD, 0x01),
+	_INIT_DCS_CMD(0xD8, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
+		      0xAA, 0xAA, 0xAA, 0xAA),
+	_INIT_DCS_CMD(0xBD, 0x02),
+	_INIT_DCS_CMD(0xD8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF,
+		      0xFF, 0xFF, 0xFF, 0xF0),
+	_INIT_DCS_CMD(0xBD, 0x00),
+	_INIT_DCS_CMD(0x11),
+	_INIT_DELAY_CMD(120),
+	_INIT_DCS_CMD(0x29),
+	_INIT_DELAY_CMD(20),
+	{},
+};
+
 static const struct panel_init_cmd ws_panel_10_1_a_4lane_init[] = {
 	_INIT_DCS_CMD(0xE0, 0x00),
 	_INIT_DCS_CMD(0xE1, 0x93),
@@ -478,6 +559,438 @@ static const struct panel_init_cmd ws_panel_10_1_a_init[] = {
 	{},
 };
 
+static const struct panel_init_cmd ws_panel_10_1_b_4lane_init[] = {
+	_INIT_DCS_CMD(0xE0, 0x00),
+	_INIT_DCS_CMD(0xE1, 0x93),
+	_INIT_DCS_CMD(0xE2, 0x65),
+	_INIT_DCS_CMD(0xE3, 0xF8),
+	_INIT_DCS_CMD(0x80, 0x03),
+	_INIT_DCS_CMD(0xE0, 0x01),
+	_INIT_DCS_CMD(0x00, 0x00),
+	_INIT_DCS_CMD(0x01, 0x3D),
+	_INIT_DCS_CMD(0x03, 0x10),
+	_INIT_DCS_CMD(0x04, 0x3F),
+	_INIT_DCS_CMD(0x17, 0x00),
+	_INIT_DCS_CMD(0x18, 0xBF),
+	_INIT_DCS_CMD(0x19, 0x01),
+	_INIT_DCS_CMD(0x1A, 0x00),
+	_INIT_DCS_CMD(0x1B, 0xBF),
+	_INIT_DCS_CMD(0x1C, 0x01),
+	_INIT_DCS_CMD(0x24, 0xFE),
+	_INIT_DCS_CMD(0x37, 0x19),
+	_INIT_DCS_CMD(0x38, 0x05),
+	_INIT_DCS_CMD(0x39, 0x08),
+	_INIT_DCS_CMD(0x3A, 0x1F),
+	_INIT_DCS_CMD(0x3C, 0x74),
+	_INIT_DCS_CMD(0x3D, 0xFF),
+	_INIT_DCS_CMD(0x3E, 0xFF),
+	_INIT_DCS_CMD(0x3F, 0xFF),
+	_INIT_DCS_CMD(0x40, 0x04),
+	_INIT_DCS_CMD(0x41, 0xA0),
+	_INIT_DCS_CMD(0x42, 0x7E),
+	_INIT_DCS_CMD(0x43, 0x1A),
+	_INIT_DCS_CMD(0x44, 0x0F),
+	_INIT_DCS_CMD(0x45, 0x24),
+	_INIT_DCS_CMD(0x55, 0x02),
+	_INIT_DCS_CMD(0x57, 0xA9),
+	_INIT_DCS_CMD(0x59, 0x0A),
+	_INIT_DCS_CMD(0x5A, 0x38),
+	_INIT_DCS_CMD(0x5B, 0x1A),
+	_INIT_DCS_CMD(0x5D, 0x7F),
+	_INIT_DCS_CMD(0x5E, 0x65),
+	_INIT_DCS_CMD(0x5F, 0x52),
+	_INIT_DCS_CMD(0x60, 0x44),
+	_INIT_DCS_CMD(0x61, 0x3D),
+	_INIT_DCS_CMD(0x62, 0x2D),
+	_INIT_DCS_CMD(0x63, 0x2D),
+	_INIT_DCS_CMD(0x64, 0x14),
+	_INIT_DCS_CMD(0x65, 0x28),
+	_INIT_DCS_CMD(0x66, 0x25),
+	_INIT_DCS_CMD(0x67, 0x23),
+	_INIT_DCS_CMD(0x68, 0x3F),
+	_INIT_DCS_CMD(0x69, 0x2D),
+	_INIT_DCS_CMD(0x6A, 0x34),
+	_INIT_DCS_CMD(0x6B, 0x27),
+	_INIT_DCS_CMD(0x6C, 0x24),
+	_INIT_DCS_CMD(0x6D, 0x18),
+	_INIT_DCS_CMD(0x6E, 0x0A),
+	_INIT_DCS_CMD(0x6F, 0x00),
+	_INIT_DCS_CMD(0x70, 0x7F),
+	_INIT_DCS_CMD(0x71, 0x65),
+	_INIT_DCS_CMD(0x72, 0x52),
+	_INIT_DCS_CMD(0x73, 0x44),
+	_INIT_DCS_CMD(0x74, 0x3D),
+	_INIT_DCS_CMD(0x75, 0x2D),
+	_INIT_DCS_CMD(0x76, 0x2D),
+	_INIT_DCS_CMD(0x77, 0x14),
+	_INIT_DCS_CMD(0x78, 0x28),
+	_INIT_DCS_CMD(0x79, 0x25),
+	_INIT_DCS_CMD(0x7A, 0x23),
+	_INIT_DCS_CMD(0x7B, 0x3F),
+	_INIT_DCS_CMD(0x7C, 0x2D),
+	_INIT_DCS_CMD(0x7D, 0x34),
+	_INIT_DCS_CMD(0x7E, 0x27),
+	_INIT_DCS_CMD(0x7F, 0x24),
+	_INIT_DCS_CMD(0x80, 0x18),
+	_INIT_DCS_CMD(0x81, 0x0A),
+	_INIT_DCS_CMD(0x82, 0x00),
+	_INIT_DCS_CMD(0xE0, 0x02),
+	_INIT_DCS_CMD(0x00, 0x51),
+	_INIT_DCS_CMD(0x01, 0x55),
+	_INIT_DCS_CMD(0x02, 0x50),
+	_INIT_DCS_CMD(0x03, 0x51),
+	_INIT_DCS_CMD(0x04, 0x5F),
+	_INIT_DCS_CMD(0x05, 0x77),
+	_INIT_DCS_CMD(0x06, 0x57),
+	_INIT_DCS_CMD(0x07, 0x5F),
+	_INIT_DCS_CMD(0x08, 0x47),
+	_INIT_DCS_CMD(0x09, 0x46),
+	_INIT_DCS_CMD(0x0A, 0x45),
+	_INIT_DCS_CMD(0x0B, 0x44),
+	_INIT_DCS_CMD(0x0C, 0x4B),
+	_INIT_DCS_CMD(0x0D, 0x4A),
+	_INIT_DCS_CMD(0x0E, 0x49),
+	_INIT_DCS_CMD(0x0F, 0x48),
+	_INIT_DCS_CMD(0x10, 0x40),
+	_INIT_DCS_CMD(0x11, 0x41),
+	_INIT_DCS_CMD(0x12, 0x5F),
+	_INIT_DCS_CMD(0x13, 0x5F),
+	_INIT_DCS_CMD(0x14, 0x5F),
+	_INIT_DCS_CMD(0x15, 0x5F),
+	_INIT_DCS_CMD(0x16, 0x51),
+	_INIT_DCS_CMD(0x17, 0x55),
+	_INIT_DCS_CMD(0x18, 0x50),
+	_INIT_DCS_CMD(0x19, 0x51),
+	_INIT_DCS_CMD(0x1A, 0x5F),
+	_INIT_DCS_CMD(0x1B, 0x77),
+	_INIT_DCS_CMD(0x1C, 0x57),
+	_INIT_DCS_CMD(0x1D, 0x5F),
+	_INIT_DCS_CMD(0x1E, 0x47),
+	_INIT_DCS_CMD(0x1F, 0x46),
+	_INIT_DCS_CMD(0x20, 0x45),
+	_INIT_DCS_CMD(0x21, 0x44),
+	_INIT_DCS_CMD(0x22, 0x4B),
+	_INIT_DCS_CMD(0x23, 0x4A),
+	_INIT_DCS_CMD(0x24, 0x49),
+	_INIT_DCS_CMD(0x25, 0x48),
+	_INIT_DCS_CMD(0x26, 0x40),
+	_INIT_DCS_CMD(0x27, 0x41),
+	_INIT_DCS_CMD(0x28, 0x5F),
+	_INIT_DCS_CMD(0x29, 0x5F),
+	_INIT_DCS_CMD(0x2A, 0x5F),
+	_INIT_DCS_CMD(0x2B, 0x5F),
+	_INIT_DCS_CMD(0x2C, 0x11),
+	_INIT_DCS_CMD(0x2D, 0x1F),
+	_INIT_DCS_CMD(0x2E, 0x01),
+	_INIT_DCS_CMD(0x2F, 0x00),
+	_INIT_DCS_CMD(0x30, 0x15),
+	_INIT_DCS_CMD(0x31, 0x17),
+	_INIT_DCS_CMD(0x32, 0x17),
+	_INIT_DCS_CMD(0x33, 0x1F),
+	_INIT_DCS_CMD(0x34, 0x08),
+	_INIT_DCS_CMD(0x35, 0x09),
+	_INIT_DCS_CMD(0x36, 0x0A),
+	_INIT_DCS_CMD(0x37, 0x0B),
+	_INIT_DCS_CMD(0x38, 0x04),
+	_INIT_DCS_CMD(0x39, 0x05),
+	_INIT_DCS_CMD(0x3A, 0x06),
+	_INIT_DCS_CMD(0x3B, 0x07),
+	_INIT_DCS_CMD(0x3C, 0x11),
+	_INIT_DCS_CMD(0x3D, 0x10),
+	_INIT_DCS_CMD(0x3E, 0x1F),
+	_INIT_DCS_CMD(0x3F, 0x1F),
+	_INIT_DCS_CMD(0x40, 0x1F),
+	_INIT_DCS_CMD(0x41, 0x1F),
+	_INIT_DCS_CMD(0x42, 0x11),
+	_INIT_DCS_CMD(0x43, 0x1F),
+	_INIT_DCS_CMD(0x44, 0x01),
+	_INIT_DCS_CMD(0x45, 0x00),
+	_INIT_DCS_CMD(0x46, 0x15),
+	_INIT_DCS_CMD(0x47, 0x17),
+	_INIT_DCS_CMD(0x48, 0x17),
+	_INIT_DCS_CMD(0x49, 0x1F),
+	_INIT_DCS_CMD(0x4A, 0x08),
+	_INIT_DCS_CMD(0x4B, 0x09),
+	_INIT_DCS_CMD(0x4C, 0x0A),
+	_INIT_DCS_CMD(0x4D, 0x0B),
+	_INIT_DCS_CMD(0x4E, 0x04),
+	_INIT_DCS_CMD(0x4F, 0x05),
+	_INIT_DCS_CMD(0x50, 0x06),
+	_INIT_DCS_CMD(0x51, 0x07),
+	_INIT_DCS_CMD(0x52, 0x11),
+	_INIT_DCS_CMD(0x53, 0x10),
+	_INIT_DCS_CMD(0x54, 0x1F),
+	_INIT_DCS_CMD(0x55, 0x1F),
+	_INIT_DCS_CMD(0x56, 0x1F),
+	_INIT_DCS_CMD(0x57, 0x1F),
+	_INIT_DCS_CMD(0x58, 0x40),
+	_INIT_DCS_CMD(0x5B, 0x10),
+	_INIT_DCS_CMD(0x5C, 0x07),
+	_INIT_DCS_CMD(0x5D, 0x40),
+	_INIT_DCS_CMD(0x5E, 0x01),
+	_INIT_DCS_CMD(0x5F, 0x02),
+	_INIT_DCS_CMD(0x60, 0x40),
+	_INIT_DCS_CMD(0x61, 0x01),
+	_INIT_DCS_CMD(0x62, 0x02),
+	_INIT_DCS_CMD(0x63, 0x06),
+	_INIT_DCS_CMD(0x64, 0x66),
+	_INIT_DCS_CMD(0x65, 0x55),
+	_INIT_DCS_CMD(0x66, 0x13),
+	_INIT_DCS_CMD(0x67, 0x73),
+	_INIT_DCS_CMD(0x68, 0x09),
+	_INIT_DCS_CMD(0x69, 0x06),
+	_INIT_DCS_CMD(0x6A, 0x66),
+	_INIT_DCS_CMD(0x6B, 0x08),
+	_INIT_DCS_CMD(0x6C, 0x00),
+	_INIT_DCS_CMD(0x6D, 0x04),
+	_INIT_DCS_CMD(0x6E, 0x04),
+	_INIT_DCS_CMD(0x6F, 0x88),
+	_INIT_DCS_CMD(0x75, 0xE3),
+	_INIT_DCS_CMD(0x76, 0x00),
+	_INIT_DCS_CMD(0x77, 0xD5),
+	_INIT_DCS_CMD(0x78, 0x2A),
+	_INIT_DCS_CMD(0x79, 0x21),
+	_INIT_DCS_CMD(0x7A, 0x00),
+	_INIT_DCS_CMD(0x7D, 0x06),
+	_INIT_DCS_CMD(0x7E, 0x66),
+	_INIT_DCS_CMD(0xE0, 0x04),
+	_INIT_DCS_CMD(0x00, 0x0E),
+	_INIT_DCS_CMD(0x02, 0xB3),
+	_INIT_DCS_CMD(0x09, 0x60),
+	_INIT_DCS_CMD(0x0E, 0x48),
+	_INIT_DCS_CMD(0x37, 0x58),
+	_INIT_DCS_CMD(0x2B, 0x0F),
+	_INIT_DCS_CMD(0xE0, 0x05),
+	_INIT_DCS_CMD(0x15, 0x1D),
+	_INIT_DCS_CMD(0xE0, 0x00),
+	_INIT_DCS_CMD(0x11),
+	_INIT_DELAY_CMD(120),
+	_INIT_DCS_CMD(0x29),
+	_INIT_DELAY_CMD(5),
+	_INIT_DCS_CMD(0x35),
+	{},
+};
+
+static const struct panel_init_cmd ws_panel_10_1_b_init[] = {
+	_INIT_DCS_CMD(0xE0, 0x00),
+	_INIT_DCS_CMD(0xE1, 0x93),
+	_INIT_DCS_CMD(0xE2, 0x65),
+	_INIT_DCS_CMD(0xE3, 0xF8),
+	_INIT_DCS_CMD(0x80, 0x01),
+	_INIT_DCS_CMD(0xE0, 0x01),
+	_INIT_DCS_CMD(0x00, 0x00),
+	_INIT_DCS_CMD(0x01, 0x3D),
+	_INIT_DCS_CMD(0x03, 0x10),
+	_INIT_DCS_CMD(0x04, 0x3F),
+	_INIT_DCS_CMD(0x17, 0x00),
+	_INIT_DCS_CMD(0x18, 0xBF),
+	_INIT_DCS_CMD(0x19, 0x01),
+	_INIT_DCS_CMD(0x1A, 0x00),
+	_INIT_DCS_CMD(0x1B, 0xBF),
+	_INIT_DCS_CMD(0x1C, 0x01),
+	_INIT_DCS_CMD(0x24, 0xFE),
+	_INIT_DCS_CMD(0x37, 0x19),
+	_INIT_DCS_CMD(0x38, 0x05),
+	_INIT_DCS_CMD(0x39, 0x08),
+	_INIT_DCS_CMD(0x3A, 0x1F),
+	_INIT_DCS_CMD(0x3C, 0x74),
+	_INIT_DCS_CMD(0x3D, 0xFF),
+	_INIT_DCS_CMD(0x3E, 0xFF),
+	_INIT_DCS_CMD(0x3F, 0xFF),
+	_INIT_DCS_CMD(0x40, 0x04),
+	_INIT_DCS_CMD(0x41, 0xA0),
+	_INIT_DCS_CMD(0x42, 0x7E),
+	_INIT_DCS_CMD(0x43, 0x1A),
+	_INIT_DCS_CMD(0x44, 0x0F),
+	_INIT_DCS_CMD(0x45, 0x24),
+	_INIT_DCS_CMD(0x55, 0x02),
+	_INIT_DCS_CMD(0x57, 0xA9),
+	_INIT_DCS_CMD(0x59, 0x0A),
+	_INIT_DCS_CMD(0x5A, 0x38),
+	_INIT_DCS_CMD(0x5B, 0x1A),
+	_INIT_DCS_CMD(0x5D, 0x7F),
+	_INIT_DCS_CMD(0x5E, 0x65),
+	_INIT_DCS_CMD(0x5F, 0x52),
+	_INIT_DCS_CMD(0x60, 0x44),
+	_INIT_DCS_CMD(0x61, 0x3D),
+	_INIT_DCS_CMD(0x62, 0x2D),
+	_INIT_DCS_CMD(0x63, 0x2D),
+	_INIT_DCS_CMD(0x64, 0x14),
+	_INIT_DCS_CMD(0x65, 0x28),
+	_INIT_DCS_CMD(0x66, 0x25),
+	_INIT_DCS_CMD(0x67, 0x23),
+	_INIT_DCS_CMD(0x68, 0x3F),
+	_INIT_DCS_CMD(0x69, 0x2D),
+	_INIT_DCS_CMD(0x6A, 0x34),
+	_INIT_DCS_CMD(0x6B, 0x27),
+	_INIT_DCS_CMD(0x6C, 0x24),
+	_INIT_DCS_CMD(0x6D, 0x18),
+	_INIT_DCS_CMD(0x6E, 0x0A),
+	_INIT_DCS_CMD(0x6F, 0x00),
+	_INIT_DCS_CMD(0x70, 0x7F),
+	_INIT_DCS_CMD(0x71, 0x65),
+	_INIT_DCS_CMD(0x72, 0x52),
+	_INIT_DCS_CMD(0x73, 0x44),
+	_INIT_DCS_CMD(0x74, 0x3D),
+	_INIT_DCS_CMD(0x75, 0x2D),
+	_INIT_DCS_CMD(0x76, 0x2D),
+	_INIT_DCS_CMD(0x77, 0x14),
+	_INIT_DCS_CMD(0x78, 0x28),
+	_INIT_DCS_CMD(0x79, 0x25),
+	_INIT_DCS_CMD(0x7A, 0x23),
+	_INIT_DCS_CMD(0x7B, 0x3F),
+	_INIT_DCS_CMD(0x7C, 0x2D),
+	_INIT_DCS_CMD(0x7D, 0x34),
+	_INIT_DCS_CMD(0x7E, 0x27),
+	_INIT_DCS_CMD(0x7F, 0x24),
+	_INIT_DCS_CMD(0x80, 0x18),
+	_INIT_DCS_CMD(0x81, 0x0A),
+	_INIT_DCS_CMD(0x82, 0x00),
+	_INIT_DCS_CMD(0xE0, 0x02),
+	_INIT_DCS_CMD(0x00, 0x51),
+	_INIT_DCS_CMD(0x01, 0x55),
+	_INIT_DCS_CMD(0x02, 0x50),
+	_INIT_DCS_CMD(0x03, 0x51),
+	_INIT_DCS_CMD(0x04, 0x5F),
+	_INIT_DCS_CMD(0x05, 0x77),
+	_INIT_DCS_CMD(0x06, 0x57),
+	_INIT_DCS_CMD(0x07, 0x5F),
+	_INIT_DCS_CMD(0x08, 0x47),
+	_INIT_DCS_CMD(0x09, 0x46),
+	_INIT_DCS_CMD(0x0A, 0x45),
+	_INIT_DCS_CMD(0x0B, 0x44),
+	_INIT_DCS_CMD(0x0C, 0x4B),
+	_INIT_DCS_CMD(0x0D, 0x4A),
+	_INIT_DCS_CMD(0x0E, 0x49),
+	_INIT_DCS_CMD(0x0F, 0x48),
+	_INIT_DCS_CMD(0x10, 0x40),
+	_INIT_DCS_CMD(0x11, 0x41),
+	_INIT_DCS_CMD(0x12, 0x5F),
+	_INIT_DCS_CMD(0x13, 0x5F),
+	_INIT_DCS_CMD(0x14, 0x5F),
+	_INIT_DCS_CMD(0x15, 0x5F),
+	_INIT_DCS_CMD(0x16, 0x51),
+	_INIT_DCS_CMD(0x17, 0x55),
+	_INIT_DCS_CMD(0x18, 0x50),
+	_INIT_DCS_CMD(0x19, 0x51),
+	_INIT_DCS_CMD(0x1A, 0x5F),
+	_INIT_DCS_CMD(0x1B, 0x77),
+	_INIT_DCS_CMD(0x1C, 0x57),
+	_INIT_DCS_CMD(0x1D, 0x5F),
+	_INIT_DCS_CMD(0x1E, 0x47),
+	_INIT_DCS_CMD(0x1F, 0x46),
+	_INIT_DCS_CMD(0x20, 0x45),
+	_INIT_DCS_CMD(0x21, 0x44),
+	_INIT_DCS_CMD(0x22, 0x4B),
+	_INIT_DCS_CMD(0x23, 0x4A),
+	_INIT_DCS_CMD(0x24, 0x49),
+	_INIT_DCS_CMD(0x25, 0x48),
+	_INIT_DCS_CMD(0x26, 0x40),
+	_INIT_DCS_CMD(0x27, 0x41),
+	_INIT_DCS_CMD(0x28, 0x5F),
+	_INIT_DCS_CMD(0x29, 0x5F),
+	_INIT_DCS_CMD(0x2A, 0x5F),
+	_INIT_DCS_CMD(0x2B, 0x5F),
+	_INIT_DCS_CMD(0x2C, 0x11),
+	_INIT_DCS_CMD(0x2D, 0x1F),
+	_INIT_DCS_CMD(0x2E, 0x01),
+	_INIT_DCS_CMD(0x2F, 0x00),
+	_INIT_DCS_CMD(0x30, 0x15),
+	_INIT_DCS_CMD(0x31, 0x17),
+	_INIT_DCS_CMD(0x32, 0x17),
+	_INIT_DCS_CMD(0x33, 0x1F),
+	_INIT_DCS_CMD(0x34, 0x08),
+	_INIT_DCS_CMD(0x35, 0x09),
+	_INIT_DCS_CMD(0x36, 0x0A),
+	_INIT_DCS_CMD(0x37, 0x0B),
+	_INIT_DCS_CMD(0x38, 0x04),
+	_INIT_DCS_CMD(0x39, 0x05),
+	_INIT_DCS_CMD(0x3A, 0x06),
+	_INIT_DCS_CMD(0x3B, 0x07),
+	_INIT_DCS_CMD(0x3C, 0x11),
+	_INIT_DCS_CMD(0x3D, 0x10),
+	_INIT_DCS_CMD(0x3E, 0x1F),
+	_INIT_DCS_CMD(0x3F, 0x1F),
+	_INIT_DCS_CMD(0x40, 0x1F),
+	_INIT_DCS_CMD(0x41, 0x1F),
+	_INIT_DCS_CMD(0x42, 0x11),
+	_INIT_DCS_CMD(0x43, 0x1F),
+	_INIT_DCS_CMD(0x44, 0x01),
+	_INIT_DCS_CMD(0x45, 0x00),
+	_INIT_DCS_CMD(0x46, 0x15),
+	_INIT_DCS_CMD(0x47, 0x17),
+	_INIT_DCS_CMD(0x48, 0x17),
+	_INIT_DCS_CMD(0x49, 0x1F),
+	_INIT_DCS_CMD(0x4A, 0x08),
+	_INIT_DCS_CMD(0x4B, 0x09),
+	_INIT_DCS_CMD(0x4C, 0x0A),
+	_INIT_DCS_CMD(0x4D, 0x0B),
+	_INIT_DCS_CMD(0x4E, 0x04),
+	_INIT_DCS_CMD(0x4F, 0x05),
+	_INIT_DCS_CMD(0x50, 0x06),
+	_INIT_DCS_CMD(0x51, 0x07),
+	_INIT_DCS_CMD(0x52, 0x11),
+	_INIT_DCS_CMD(0x53, 0x10),
+	_INIT_DCS_CMD(0x54, 0x1F),
+	_INIT_DCS_CMD(0x55, 0x1F),
+	_INIT_DCS_CMD(0x56, 0x1F),
+	_INIT_DCS_CMD(0x57, 0x1F),
+	_INIT_DCS_CMD(0x58, 0x40),
+	_INIT_DCS_CMD(0x5B, 0x10),
+	_INIT_DCS_CMD(0x5C, 0x07),
+	_INIT_DCS_CMD(0x5D, 0x40),
+	_INIT_DCS_CMD(0x5E, 0x01),
+	_INIT_DCS_CMD(0x5F, 0x02),
+	_INIT_DCS_CMD(0x60, 0x40),
+	_INIT_DCS_CMD(0x61, 0x01),
+	_INIT_DCS_CMD(0x62, 0x02),
+	_INIT_DCS_CMD(0x63, 0x06),
+	_INIT_DCS_CMD(0x64, 0x66),
+	_INIT_DCS_CMD(0x65, 0x55),
+	_INIT_DCS_CMD(0x66, 0x13),
+	_INIT_DCS_CMD(0x67, 0x73),
+	_INIT_DCS_CMD(0x68, 0x09),
+	_INIT_DCS_CMD(0x69, 0x06),
+	_INIT_DCS_CMD(0x6A, 0x66),
+	_INIT_DCS_CMD(0x6B, 0x08),
+	_INIT_DCS_CMD(0x6C, 0x00),
+	_INIT_DCS_CMD(0x6D, 0x04),
+	_INIT_DCS_CMD(0x6E, 0x04),
+	_INIT_DCS_CMD(0x6F, 0x88),
+	_INIT_DCS_CMD(0x75, 0xE3),
+	_INIT_DCS_CMD(0x76, 0x00),
+	_INIT_DCS_CMD(0x77, 0xD5),
+	_INIT_DCS_CMD(0x78, 0x2A),
+	_INIT_DCS_CMD(0x79, 0x21),
+	_INIT_DCS_CMD(0x7A, 0x00),
+	_INIT_DCS_CMD(0x7D, 0x06),
+	_INIT_DCS_CMD(0x7E, 0x66),
+	_INIT_DCS_CMD(0xE0, 0x04),
+	_INIT_DCS_CMD(0x00, 0x0E),
+	_INIT_DCS_CMD(0x02, 0xB3),
+	_INIT_DCS_CMD(0x09, 0x60),
+	_INIT_DCS_CMD(0x0E, 0x48),
+	_INIT_DCS_CMD(0x37, 0x58),
+	_INIT_DCS_CMD(0x2B, 0x0F),
+	_INIT_DCS_CMD(0xE0, 0x05),
+	_INIT_DCS_CMD(0x15, 0x1D),
+	_INIT_DCS_CMD(0xE0, 0x00),
+	_INIT_DCS_CMD(0x11),
+	_INIT_DELAY_CMD(120),
+	_INIT_DCS_CMD(0x29),
+	_INIT_DELAY_CMD(5),
+	_INIT_DCS_CMD(0x35),
+	{},
+};
+
+static const struct panel_init_cmd ws_panel_8_8_a_init[] = {
+	_INIT_DCS_CMD(0x11),
+	_INIT_DELAY_CMD(120),
+	_INIT_DCS_CMD(0x29),
+	_INIT_DELAY_CMD(50),
+	{},
+};
+
 static const struct panel_init_cmd ws_panel_8_a_4lane_init[] = {
 	_INIT_DCS_CMD(0xE0, 0x00), _INIT_DCS_CMD(0xE1, 0x93),
 	_INIT_DCS_CMD(0xE2, 0x65), _INIT_DCS_CMD(0xE3, 0xF8),
@@ -958,6 +1471,212 @@ static const struct panel_init_cmd ws_panel_5_a_init[] = {
 	{},
 };
 
+static const struct panel_init_cmd ws_panel_4_c_init[] = {
+	_INIT_DCS_CMD(0xE0, 0x00), _INIT_DCS_CMD(0xE1, 0x93),
+	_INIT_DCS_CMD(0xE2, 0x65), _INIT_DCS_CMD(0xE3, 0xF8),
+	_INIT_DCS_CMD(0x80, 0x01), _INIT_DCS_CMD(0xE0, 0x01),
+	_INIT_DCS_CMD(0x00, 0x00), _INIT_DCS_CMD(0x01, 0x41),
+	_INIT_DCS_CMD(0x03, 0x10), _INIT_DCS_CMD(0x04, 0x44),
+	_INIT_DCS_CMD(0x17, 0x00), _INIT_DCS_CMD(0x18, 0xD0),
+	_INIT_DCS_CMD(0x19, 0x00), _INIT_DCS_CMD(0x1A, 0x00),
+	_INIT_DCS_CMD(0x1B, 0xD0), _INIT_DCS_CMD(0x1C, 0x00),
+	_INIT_DCS_CMD(0x24, 0xFE), _INIT_DCS_CMD(0x35, 0x26),
+	_INIT_DCS_CMD(0x37, 0x09), _INIT_DCS_CMD(0x38, 0x04),
+	_INIT_DCS_CMD(0x39, 0x08), _INIT_DCS_CMD(0x3A, 0x0A),
+	_INIT_DCS_CMD(0x3C, 0x78), _INIT_DCS_CMD(0x3D, 0xFF),
+	_INIT_DCS_CMD(0x3E, 0xFF), _INIT_DCS_CMD(0x3F, 0xFF),
+	_INIT_DCS_CMD(0x40, 0x04), _INIT_DCS_CMD(0x41, 0x64),
+	_INIT_DCS_CMD(0x42, 0xC7), _INIT_DCS_CMD(0x43, 0x18),
+	_INIT_DCS_CMD(0x44, 0x0B), _INIT_DCS_CMD(0x45, 0x14),
+	_INIT_DCS_CMD(0x55, 0x02), _INIT_DCS_CMD(0x57, 0x49),
+	_INIT_DCS_CMD(0x59, 0x0A), _INIT_DCS_CMD(0x5A, 0x1B),
+	_INIT_DCS_CMD(0x5B, 0x19), _INIT_DCS_CMD(0x5D, 0x7F),
+	_INIT_DCS_CMD(0x5E, 0x56), _INIT_DCS_CMD(0x5F, 0x43),
+	_INIT_DCS_CMD(0x60, 0x37), _INIT_DCS_CMD(0x61, 0x33),
+	_INIT_DCS_CMD(0x62, 0x25), _INIT_DCS_CMD(0x63, 0x2A),
+	_INIT_DCS_CMD(0x64, 0x16), _INIT_DCS_CMD(0x65, 0x30),
+	_INIT_DCS_CMD(0x66, 0x2F), _INIT_DCS_CMD(0x67, 0x32),
+	_INIT_DCS_CMD(0x68, 0x53), _INIT_DCS_CMD(0x69, 0x43),
+	_INIT_DCS_CMD(0x6A, 0x4C), _INIT_DCS_CMD(0x6B, 0x40),
+	_INIT_DCS_CMD(0x6C, 0x3D), _INIT_DCS_CMD(0x6D, 0x31),
+	_INIT_DCS_CMD(0x6E, 0x20), _INIT_DCS_CMD(0x6F, 0x0F),
+	_INIT_DCS_CMD(0x70, 0x7F), _INIT_DCS_CMD(0x71, 0x56),
+	_INIT_DCS_CMD(0x72, 0x43), _INIT_DCS_CMD(0x73, 0x37),
+	_INIT_DCS_CMD(0x74, 0x33), _INIT_DCS_CMD(0x75, 0x25),
+	_INIT_DCS_CMD(0x76, 0x2A), _INIT_DCS_CMD(0x77, 0x16),
+	_INIT_DCS_CMD(0x78, 0x30), _INIT_DCS_CMD(0x79, 0x2F),
+	_INIT_DCS_CMD(0x7A, 0x32), _INIT_DCS_CMD(0x7B, 0x53),
+	_INIT_DCS_CMD(0x7C, 0x43), _INIT_DCS_CMD(0x7D, 0x4C),
+	_INIT_DCS_CMD(0x7E, 0x40), _INIT_DCS_CMD(0x7F, 0x3D),
+	_INIT_DCS_CMD(0x80, 0x31), _INIT_DCS_CMD(0x81, 0x20),
+	_INIT_DCS_CMD(0x82, 0x0F), _INIT_DCS_CMD(0xE0, 0x02),
+	_INIT_DCS_CMD(0x00, 0x5F), _INIT_DCS_CMD(0x01, 0x5F),
+	_INIT_DCS_CMD(0x02, 0x5E), _INIT_DCS_CMD(0x03, 0x5E),
+	_INIT_DCS_CMD(0x04, 0x50), _INIT_DCS_CMD(0x05, 0x48),
+	_INIT_DCS_CMD(0x06, 0x48), _INIT_DCS_CMD(0x07, 0x4A),
+	_INIT_DCS_CMD(0x08, 0x4A), _INIT_DCS_CMD(0x09, 0x44),
+	_INIT_DCS_CMD(0x0A, 0x44), _INIT_DCS_CMD(0x0B, 0x46),
+	_INIT_DCS_CMD(0x0C, 0x46), _INIT_DCS_CMD(0x0D, 0x5F),
+	_INIT_DCS_CMD(0x0E, 0x5F), _INIT_DCS_CMD(0x0F, 0x57),
+	_INIT_DCS_CMD(0x10, 0x57), _INIT_DCS_CMD(0x11, 0x77),
+	_INIT_DCS_CMD(0x12, 0x77), _INIT_DCS_CMD(0x13, 0x40),
+	_INIT_DCS_CMD(0x14, 0x42), _INIT_DCS_CMD(0x15, 0x5F),
+	_INIT_DCS_CMD(0x16, 0x5F), _INIT_DCS_CMD(0x17, 0x5F),
+	_INIT_DCS_CMD(0x18, 0x5E), _INIT_DCS_CMD(0x19, 0x5E),
+	_INIT_DCS_CMD(0x1A, 0x50), _INIT_DCS_CMD(0x1B, 0x49),
+	_INIT_DCS_CMD(0x1C, 0x49), _INIT_DCS_CMD(0x1D, 0x4B),
+	_INIT_DCS_CMD(0x1E, 0x4B), _INIT_DCS_CMD(0x1F, 0x45),
+	_INIT_DCS_CMD(0x20, 0x45), _INIT_DCS_CMD(0x21, 0x47),
+	_INIT_DCS_CMD(0x22, 0x47), _INIT_DCS_CMD(0x23, 0x5F),
+	_INIT_DCS_CMD(0x24, 0x5F), _INIT_DCS_CMD(0x25, 0x57),
+	_INIT_DCS_CMD(0x26, 0x57), _INIT_DCS_CMD(0x27, 0x77),
+	_INIT_DCS_CMD(0x28, 0x77), _INIT_DCS_CMD(0x29, 0x41),
+	_INIT_DCS_CMD(0x2A, 0x43), _INIT_DCS_CMD(0x2B, 0x5F),
+	_INIT_DCS_CMD(0x2C, 0x1E), _INIT_DCS_CMD(0x2D, 0x1E),
+	_INIT_DCS_CMD(0x2E, 0x1F), _INIT_DCS_CMD(0x2F, 0x1F),
+	_INIT_DCS_CMD(0x30, 0x10), _INIT_DCS_CMD(0x31, 0x07),
+	_INIT_DCS_CMD(0x32, 0x07), _INIT_DCS_CMD(0x33, 0x05),
+	_INIT_DCS_CMD(0x34, 0x05), _INIT_DCS_CMD(0x35, 0x0B),
+	_INIT_DCS_CMD(0x36, 0x0B), _INIT_DCS_CMD(0x37, 0x09),
+	_INIT_DCS_CMD(0x38, 0x09), _INIT_DCS_CMD(0x39, 0x1F),
+	_INIT_DCS_CMD(0x3A, 0x1F), _INIT_DCS_CMD(0x3B, 0x17),
+	_INIT_DCS_CMD(0x3C, 0x17), _INIT_DCS_CMD(0x3D, 0x17),
+	_INIT_DCS_CMD(0x3E, 0x17), _INIT_DCS_CMD(0x3F, 0x03),
+	_INIT_DCS_CMD(0x40, 0x01), _INIT_DCS_CMD(0x41, 0x1F),
+	_INIT_DCS_CMD(0x42, 0x1E), _INIT_DCS_CMD(0x43, 0x1E),
+	_INIT_DCS_CMD(0x44, 0x1F), _INIT_DCS_CMD(0x45, 0x1F),
+	_INIT_DCS_CMD(0x46, 0x10), _INIT_DCS_CMD(0x47, 0x06),
+	_INIT_DCS_CMD(0x48, 0x06), _INIT_DCS_CMD(0x49, 0x04),
+	_INIT_DCS_CMD(0x4A, 0x04), _INIT_DCS_CMD(0x4B, 0x0A),
+	_INIT_DCS_CMD(0x4C, 0x0A), _INIT_DCS_CMD(0x4D, 0x08),
+	_INIT_DCS_CMD(0x4E, 0x08), _INIT_DCS_CMD(0x4F, 0x1F),
+	_INIT_DCS_CMD(0x50, 0x1F), _INIT_DCS_CMD(0x51, 0x17),
+	_INIT_DCS_CMD(0x52, 0x17), _INIT_DCS_CMD(0x53, 0x17),
+	_INIT_DCS_CMD(0x54, 0x17), _INIT_DCS_CMD(0x55, 0x02),
+	_INIT_DCS_CMD(0x56, 0x00), _INIT_DCS_CMD(0x57, 0x1F),
+	_INIT_DCS_CMD(0xE0, 0x02), _INIT_DCS_CMD(0x58, 0x40),
+	_INIT_DCS_CMD(0x59, 0x00), _INIT_DCS_CMD(0x5A, 0x00),
+	_INIT_DCS_CMD(0x5B, 0x30), _INIT_DCS_CMD(0x5C, 0x01),
+	_INIT_DCS_CMD(0x5D, 0x30), _INIT_DCS_CMD(0x5E, 0x01),
+	_INIT_DCS_CMD(0x5F, 0x02), _INIT_DCS_CMD(0x60, 0x30),
+	_INIT_DCS_CMD(0x61, 0x03), _INIT_DCS_CMD(0x62, 0x04),
+	_INIT_DCS_CMD(0x63, 0x04), _INIT_DCS_CMD(0x64, 0xA6),
+	_INIT_DCS_CMD(0x65, 0x43), _INIT_DCS_CMD(0x66, 0x30),
+	_INIT_DCS_CMD(0x67, 0x73), _INIT_DCS_CMD(0x68, 0x05),
+	_INIT_DCS_CMD(0x69, 0x04), _INIT_DCS_CMD(0x6A, 0x7F),
+	_INIT_DCS_CMD(0x6B, 0x08), _INIT_DCS_CMD(0x6C, 0x00),
+	_INIT_DCS_CMD(0x6D, 0x04), _INIT_DCS_CMD(0x6E, 0x04),
+	_INIT_DCS_CMD(0x6F, 0x88), _INIT_DCS_CMD(0x75, 0xD9),
+	_INIT_DCS_CMD(0x76, 0x00), _INIT_DCS_CMD(0x77, 0x33),
+	_INIT_DCS_CMD(0x78, 0x43), _INIT_DCS_CMD(0xE0, 0x00),
+	_INIT_DCS_CMD(0x11),	   _INIT_DELAY_CMD(120),
+	_INIT_DCS_CMD(0x29),	   _INIT_DELAY_CMD(5),
+	_INIT_DCS_CMD(0x35, 0x00), {},
+};
+
+static const struct panel_init_cmd ws_panel_3_4_c_init[] = {
+	_INIT_DCS_CMD(0xE0, 0x00), _INIT_DCS_CMD(0xE1, 0x93),
+	_INIT_DCS_CMD(0xE2, 0x65), _INIT_DCS_CMD(0xE3, 0xF8),
+	_INIT_DCS_CMD(0x80, 0x01), _INIT_DCS_CMD(0xE0, 0x01),
+	_INIT_DCS_CMD(0x00, 0x00), _INIT_DCS_CMD(0x01, 0x41),
+	_INIT_DCS_CMD(0x03, 0x10), _INIT_DCS_CMD(0x04, 0x44),
+	_INIT_DCS_CMD(0x17, 0x00), _INIT_DCS_CMD(0x18, 0xD0),
+	_INIT_DCS_CMD(0x19, 0x00), _INIT_DCS_CMD(0x1A, 0x00),
+	_INIT_DCS_CMD(0x1B, 0xD0), _INIT_DCS_CMD(0x1C, 0x00),
+	_INIT_DCS_CMD(0x24, 0xFE), _INIT_DCS_CMD(0x35, 0x26),
+	_INIT_DCS_CMD(0x37, 0x09), _INIT_DCS_CMD(0x38, 0x04),
+	_INIT_DCS_CMD(0x39, 0x08), _INIT_DCS_CMD(0x3A, 0x0A),
+	_INIT_DCS_CMD(0x3C, 0x78), _INIT_DCS_CMD(0x3D, 0xFF),
+	_INIT_DCS_CMD(0x3E, 0xFF), _INIT_DCS_CMD(0x3F, 0xFF),
+	_INIT_DCS_CMD(0x40, 0x00), _INIT_DCS_CMD(0x41, 0x64),
+	_INIT_DCS_CMD(0x42, 0xC7), _INIT_DCS_CMD(0x43, 0x18),
+	_INIT_DCS_CMD(0x44, 0x0B), _INIT_DCS_CMD(0x45, 0x14),
+	_INIT_DCS_CMD(0x55, 0x02), _INIT_DCS_CMD(0x57, 0x49),
+	_INIT_DCS_CMD(0x59, 0x0A), _INIT_DCS_CMD(0x5A, 0x1B),
+	_INIT_DCS_CMD(0x5B, 0x19), _INIT_DCS_CMD(0x5D, 0x7F),
+	_INIT_DCS_CMD(0x5E, 0x56), _INIT_DCS_CMD(0x5F, 0x43),
+	_INIT_DCS_CMD(0x60, 0x37), _INIT_DCS_CMD(0x61, 0x33),
+	_INIT_DCS_CMD(0x62, 0x25), _INIT_DCS_CMD(0x63, 0x2A),
+	_INIT_DCS_CMD(0x64, 0x16), _INIT_DCS_CMD(0x65, 0x30),
+	_INIT_DCS_CMD(0x66, 0x2F), _INIT_DCS_CMD(0x67, 0x32),
+	_INIT_DCS_CMD(0x68, 0x53), _INIT_DCS_CMD(0x69, 0x43),
+	_INIT_DCS_CMD(0x6A, 0x4C), _INIT_DCS_CMD(0x6B, 0x40),
+	_INIT_DCS_CMD(0x6C, 0x3D), _INIT_DCS_CMD(0x6D, 0x31),
+	_INIT_DCS_CMD(0x6E, 0x20), _INIT_DCS_CMD(0x6F, 0x0F),
+	_INIT_DCS_CMD(0x70, 0x7F), _INIT_DCS_CMD(0x71, 0x56),
+	_INIT_DCS_CMD(0x72, 0x43), _INIT_DCS_CMD(0x73, 0x37),
+	_INIT_DCS_CMD(0x74, 0x33), _INIT_DCS_CMD(0x75, 0x25),
+	_INIT_DCS_CMD(0x76, 0x2A), _INIT_DCS_CMD(0x77, 0x16),
+	_INIT_DCS_CMD(0x78, 0x30), _INIT_DCS_CMD(0x79, 0x2F),
+	_INIT_DCS_CMD(0x7A, 0x32), _INIT_DCS_CMD(0x7B, 0x53),
+	_INIT_DCS_CMD(0x7C, 0x43), _INIT_DCS_CMD(0x7D, 0x4C),
+	_INIT_DCS_CMD(0x7E, 0x40), _INIT_DCS_CMD(0x7F, 0x3D),
+	_INIT_DCS_CMD(0x80, 0x31), _INIT_DCS_CMD(0x81, 0x20),
+	_INIT_DCS_CMD(0x82, 0x0F), _INIT_DCS_CMD(0xE0, 0x02),
+	_INIT_DCS_CMD(0x00, 0x5F), _INIT_DCS_CMD(0x01, 0x5F),
+	_INIT_DCS_CMD(0x02, 0x5E), _INIT_DCS_CMD(0x03, 0x5E),
+	_INIT_DCS_CMD(0x04, 0x50), _INIT_DCS_CMD(0x05, 0x48),
+	_INIT_DCS_CMD(0x06, 0x48), _INIT_DCS_CMD(0x07, 0x4A),
+	_INIT_DCS_CMD(0x08, 0x4A), _INIT_DCS_CMD(0x09, 0x44),
+	_INIT_DCS_CMD(0x0A, 0x44), _INIT_DCS_CMD(0x0B, 0x46),
+	_INIT_DCS_CMD(0x0C, 0x46), _INIT_DCS_CMD(0x0D, 0x5F),
+	_INIT_DCS_CMD(0x0E, 0x5F), _INIT_DCS_CMD(0x0F, 0x57),
+	_INIT_DCS_CMD(0x10, 0x57), _INIT_DCS_CMD(0x11, 0x77),
+	_INIT_DCS_CMD(0x12, 0x77), _INIT_DCS_CMD(0x13, 0x40),
+	_INIT_DCS_CMD(0x14, 0x42), _INIT_DCS_CMD(0x15, 0x5F),
+	_INIT_DCS_CMD(0x16, 0x5F), _INIT_DCS_CMD(0x17, 0x5F),
+	_INIT_DCS_CMD(0x18, 0x5E), _INIT_DCS_CMD(0x19, 0x5E),
+	_INIT_DCS_CMD(0x1A, 0x50), _INIT_DCS_CMD(0x1B, 0x49),
+	_INIT_DCS_CMD(0x1C, 0x49), _INIT_DCS_CMD(0x1D, 0x4B),
+	_INIT_DCS_CMD(0x1E, 0x4B), _INIT_DCS_CMD(0x1F, 0x45),
+	_INIT_DCS_CMD(0x20, 0x45), _INIT_DCS_CMD(0x21, 0x47),
+	_INIT_DCS_CMD(0x22, 0x47), _INIT_DCS_CMD(0x23, 0x5F),
+	_INIT_DCS_CMD(0x24, 0x5F), _INIT_DCS_CMD(0x25, 0x57),
+	_INIT_DCS_CMD(0x26, 0x57), _INIT_DCS_CMD(0x27, 0x77),
+	_INIT_DCS_CMD(0x28, 0x77), _INIT_DCS_CMD(0x29, 0x41),
+	_INIT_DCS_CMD(0x2A, 0x43), _INIT_DCS_CMD(0x2B, 0x5F),
+	_INIT_DCS_CMD(0x2C, 0x1E), _INIT_DCS_CMD(0x2D, 0x1E),
+	_INIT_DCS_CMD(0x2E, 0x1F), _INIT_DCS_CMD(0x2F, 0x1F),
+	_INIT_DCS_CMD(0x30, 0x10), _INIT_DCS_CMD(0x31, 0x07),
+	_INIT_DCS_CMD(0x32, 0x07), _INIT_DCS_CMD(0x33, 0x05),
+	_INIT_DCS_CMD(0x34, 0x05), _INIT_DCS_CMD(0x35, 0x0B),
+	_INIT_DCS_CMD(0x36, 0x0B), _INIT_DCS_CMD(0x37, 0x09),
+	_INIT_DCS_CMD(0x38, 0x09), _INIT_DCS_CMD(0x39, 0x1F),
+	_INIT_DCS_CMD(0x3A, 0x1F), _INIT_DCS_CMD(0x3B, 0x17),
+	_INIT_DCS_CMD(0x3C, 0x17), _INIT_DCS_CMD(0x3D, 0x17),
+	_INIT_DCS_CMD(0x3E, 0x17), _INIT_DCS_CMD(0x3F, 0x03),
+	_INIT_DCS_CMD(0x40, 0x01), _INIT_DCS_CMD(0x41, 0x1F),
+	_INIT_DCS_CMD(0x42, 0x1E), _INIT_DCS_CMD(0x43, 0x1E),
+	_INIT_DCS_CMD(0x44, 0x1F), _INIT_DCS_CMD(0x45, 0x1F),
+	_INIT_DCS_CMD(0x46, 0x10), _INIT_DCS_CMD(0x47, 0x06),
+	_INIT_DCS_CMD(0x48, 0x06), _INIT_DCS_CMD(0x49, 0x04),
+	_INIT_DCS_CMD(0x4A, 0x04), _INIT_DCS_CMD(0x4B, 0x0A),
+	_INIT_DCS_CMD(0x4C, 0x0A), _INIT_DCS_CMD(0x4D, 0x08),
+	_INIT_DCS_CMD(0x4E, 0x08), _INIT_DCS_CMD(0x4F, 0x1F),
+	_INIT_DCS_CMD(0x50, 0x1F), _INIT_DCS_CMD(0x51, 0x17),
+	_INIT_DCS_CMD(0x52, 0x17), _INIT_DCS_CMD(0x53, 0x17),
+	_INIT_DCS_CMD(0x54, 0x17), _INIT_DCS_CMD(0x55, 0x02),
+	_INIT_DCS_CMD(0x56, 0x00), _INIT_DCS_CMD(0x57, 0x1F),
+	_INIT_DCS_CMD(0xE0, 0x02), _INIT_DCS_CMD(0x58, 0x40),
+	_INIT_DCS_CMD(0x59, 0x00), _INIT_DCS_CMD(0x5A, 0x00),
+	_INIT_DCS_CMD(0x5B, 0x30), _INIT_DCS_CMD(0x5C, 0x01),
+	_INIT_DCS_CMD(0x5D, 0x30), _INIT_DCS_CMD(0x5E, 0x01),
+	_INIT_DCS_CMD(0x5F, 0x02), _INIT_DCS_CMD(0x60, 0x30),
+	_INIT_DCS_CMD(0x61, 0x03), _INIT_DCS_CMD(0x62, 0x04),
+	_INIT_DCS_CMD(0x63, 0x04), _INIT_DCS_CMD(0x64, 0xA6),
+	_INIT_DCS_CMD(0x65, 0x43), _INIT_DCS_CMD(0x66, 0x30),
+	_INIT_DCS_CMD(0x67, 0x73), _INIT_DCS_CMD(0x68, 0x05),
+	_INIT_DCS_CMD(0x69, 0x04), _INIT_DCS_CMD(0x6A, 0x7F),
+	_INIT_DCS_CMD(0x6B, 0x08), _INIT_DCS_CMD(0x6C, 0x00),
+	_INIT_DCS_CMD(0x6D, 0x04), _INIT_DCS_CMD(0x6E, 0x04),
+	_INIT_DCS_CMD(0x6F, 0x88), _INIT_DCS_CMD(0x75, 0xD9),
+	_INIT_DCS_CMD(0x76, 0x00), _INIT_DCS_CMD(0x77, 0x33),
+	_INIT_DCS_CMD(0x78, 0x43), _INIT_DCS_CMD(0xE0, 0x00),
+	_INIT_DCS_CMD(0x11),	   _INIT_DELAY_CMD(120),
+	_INIT_DCS_CMD(0x29),	   _INIT_DELAY_CMD(5),
+	_INIT_DCS_CMD(0x35, 0x00), {},
+};
+
 static inline struct ws_panel *panel_to_ws(struct drm_panel *panel)
 {
 	return container_of(panel, struct ws_panel, panel);
@@ -1007,6 +1726,16 @@ static int ws_panel_prepare(struct drm_panel *panel)
 	struct ws_panel *ctx = panel_to_ws(panel);
 	int ret;
 
+	if (ctx->iovcc) {
+		gpiod_set_value_cansleep(ctx->iovcc, 1);
+		msleep(20);
+	}
+
+	if (ctx->avdd) {
+		gpiod_set_value_cansleep(ctx->avdd, 1);
+		msleep(20);
+	}
+
 	/* And reset it */
 	if (ctx->reset) {
 		gpiod_set_value_cansleep(ctx->reset, 0);
@@ -1029,12 +1758,38 @@ static int ws_panel_unprepare(struct drm_panel *panel)
 	mipi_dsi_dcs_set_display_off(ctx->dsi);
 	mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
 
-	if (ctx->reset)
+	if (ctx->reset) {
 		gpiod_set_value_cansleep(ctx->reset, 0);
+		msleep(20);
+	}
+
+	if (ctx->avdd) {
+		gpiod_set_value_cansleep(ctx->avdd, 0);
+		msleep(20);
+	}
+
+	if (ctx->iovcc) {
+		gpiod_set_value_cansleep(ctx->iovcc, 0);
+		msleep(20);
+	}
 
 	return 0;
 }
 
+static const struct drm_display_mode ws_panel_12_3_a_4lane_mode = {
+	.clock = 95000,
+	.hdisplay = 720,
+	.hsync_start = 720 + 10,
+	.hsync_end = 720 + 10 + 10,
+	.htotal = 720 + 10 + 10 + 12,
+	.vdisplay = 1920,
+	.vsync_start = 1920 + 64,
+	.vsync_end = 1920 + 64 + 18,
+	.vtotal = 1920 + 64 + 18 + 4,
+	.width_mm = 109,
+	.height_mm = 292,
+};
+
 static const struct drm_display_mode ws_panel_10_1_a_mode = {
 	.clock = 70000,
 	.hdisplay = 800,
@@ -1049,6 +1804,76 @@ static const struct drm_display_mode ws_panel_10_1_a_mode = {
 	.height_mm = 216,
 };
 
+static const struct drm_display_mode ws_panel_10_1_b_4lane_mode = {
+	.clock = 66000,
+	.hdisplay = 720,
+	.hsync_start = 720 + 60,
+	.hsync_end = 720 + 60 + 60,
+	.htotal = 720 + 60 + 60 + 4,
+	.vdisplay = 1280,
+	.vsync_start = 1280 + 16,
+	.vsync_end = 1280 + 16 + 12,
+	.vtotal = 1280 + 16 + 12 + 4,
+	.width_mm = 125,
+	.height_mm = 222,
+};
+
+static const struct drm_display_mode ws_panel_10_1_b_mode = {
+	.clock = 69000,
+	.hdisplay = 720,
+	.hsync_start = 720 + 50,
+	.hsync_end = 720 + 50 + 50,
+	.htotal = 720 + 50 + 50 + 50,
+	.vdisplay = 1280,
+	.vsync_start = 1280 + 26,
+	.vsync_end = 1280 + 26 + 12,
+	.vtotal = 1280 + 26 + 12 + 4,
+	.width_mm = 125,
+	.height_mm = 222,
+};
+
+static const struct drm_display_mode ws_panel_9_b_4lane_mode = {
+	.clock = 66000,
+	.hdisplay = 720,
+	.hsync_start = 720 + 60,
+	.hsync_end = 720 + 60 + 60,
+	.htotal = 720 + 60 + 60 + 4,
+	.vdisplay = 1280,
+	.vsync_start = 1280 + 16,
+	.vsync_end = 1280 + 16 + 12,
+	.vtotal = 1280 + 16 + 12 + 4,
+	.width_mm = 114,
+	.height_mm = 196,
+};
+
+static const struct drm_display_mode ws_panel_9_b_mode = {
+	.clock = 69000,
+	.hdisplay = 720,
+	.hsync_start = 720 + 50,
+	.hsync_end = 720 + 50 + 50,
+	.htotal = 720 + 50 + 50 + 50,
+	.vdisplay = 1280,
+	.vsync_start = 1280 + 26,
+	.vsync_end = 1280 + 26 + 12,
+	.vtotal = 1280 + 26 + 12 + 4,
+	.width_mm = 114,
+	.height_mm = 196,
+};
+
+static const struct drm_display_mode ws_panel_8_8_a_mode = {
+	.clock = 75000,
+	.hdisplay = 480,
+	.hsync_start = 480 + 50,
+	.hsync_end = 480 + 50 + 50,
+	.htotal = 480 + 50 + 50 + 50,
+	.vdisplay = 1920,
+	.vsync_start = 1920 + 20,
+	.vsync_end = 1920 + 20 + 20,
+	.vtotal = 1920 + 20 + 20 + 20,
+	.width_mm = 68,
+	.height_mm = 219,
+};
+
 static const struct drm_display_mode ws_panel_8_a_mode = {
 	.clock = 70000,
 	.hdisplay = 800,
@@ -1092,7 +1917,7 @@ static const struct drm_display_mode ws_panel_5_5_a_mode = {
 };
 
 static const struct drm_display_mode ws_panel_5_a_mode = {
-	.clock = 63000,
+	.clock = 70000,
 	.hdisplay = 720,
 	.hsync_start = 720 + 40,
 	.hsync_end = 720 + 40 + 20,
@@ -1105,6 +1930,34 @@ static const struct drm_display_mode ws_panel_5_a_mode = {
 	.height_mm = 110,
 };
 
+static const struct drm_display_mode ws_panel_4_c_mode = {
+	.clock = 36500,
+	.hdisplay = 720,
+	.hsync_start = 720 + 40,
+	.hsync_end = 720 + 40 + 20,
+	.htotal = 720 + 40 + 20 + 20,
+	.vdisplay = 720,
+	.vsync_start = 720 + 24,
+	.vsync_end = 720 + 24 + 4,
+	.vtotal = 720 + 24 + 4 + 12,
+	.width_mm = 88,
+	.height_mm = 88,
+};
+
+static const struct drm_display_mode ws_panel_3_4_c_mode = {
+	.clock = 44300,
+	.hdisplay = 800,
+	.hsync_start = 800 + 40,
+	.hsync_end = 800 + 40 + 20,
+	.htotal = 800 + 40 + 20 + 20,
+	.vdisplay = 800,
+	.vsync_start = 800 + 24,
+	.vsync_end = 800 + 24 + 4,
+	.vtotal = 800 + 24 + 4 + 12,
+	.width_mm = 88,
+	.height_mm = 88,
+};
+
 static int ws_panel_get_modes(struct drm_panel *panel,
 			      struct drm_connector *connector)
 {
@@ -1171,6 +2024,16 @@ static int ws_panel_dsi_probe(struct mipi_dsi_device *dsi)
 		return dev_err_probe(&dsi->dev, PTR_ERR(ctx->reset),
 				     "Couldn't get our reset GPIO\n");
 
+	ctx->iovcc = devm_gpiod_get_optional(&dsi->dev, "iovcc", GPIOD_OUT_LOW);
+	if (IS_ERR(ctx->iovcc))
+		return dev_err_probe(&dsi->dev, PTR_ERR(ctx->iovcc),
+				     "Couldn't get our iovcc GPIO\n");
+
+	ctx->avdd = devm_gpiod_get_optional(&dsi->dev, "avdd", GPIOD_OUT_LOW);
+	if (IS_ERR(ctx->avdd))
+		return dev_err_probe(&dsi->dev, PTR_ERR(ctx->avdd),
+				     "Couldn't get our avdd GPIO\n");
+
 	ret = of_drm_get_panel_orientation(dsi->dev.of_node, &ctx->orientation);
 	if (ret) {
 		dev_err(&dsi->dev, "%pOF: failed to get orientation: %d\n",
@@ -1202,8 +2065,20 @@ static void ws_panel_dsi_remove(struct mipi_dsi_device *dsi)
 
 	mipi_dsi_detach(dsi);
 	drm_panel_remove(&ctx->panel);
-	if (ctx->reset)
+	if (ctx->reset) {
 		gpiod_set_value_cansleep(ctx->reset, 0);
+		msleep(20);
+	}
+
+	if (ctx->avdd) {
+		gpiod_set_value_cansleep(ctx->avdd, 0);
+		msleep(20);
+	}
+
+	if (ctx->iovcc) {
+		gpiod_set_value_cansleep(ctx->iovcc, 0);
+		msleep(20);
+	}
 }
 
 static void ws_panel_dsi_shutdown(struct mipi_dsi_device *dsi)
@@ -1213,9 +2088,29 @@ static void ws_panel_dsi_shutdown(struct mipi_dsi_device *dsi)
 	if (ctx->reset) {
 		dev_info(&dsi->dev, "shutdown\n");
 		gpiod_set_value_cansleep(ctx->reset, 0);
+		msleep(20);
+	}
+
+	if (ctx->avdd) {
+		gpiod_set_value_cansleep(ctx->avdd, 0);
+		msleep(20);
+	}
+
+	if (ctx->iovcc) {
+		gpiod_set_value_cansleep(ctx->iovcc, 0);
+		msleep(20);
 	}
 }
 
+static const struct ws_panel_desc ws_panel_12_3_inch_a_4lane_desc = {
+	.init = ws_panel_12_3_a_4lane_init,
+	.mode = &ws_panel_12_3_a_4lane_mode,
+	.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+		      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.lanes = 4,
+	.format = MIPI_DSI_FMT_RGB888,
+};
+
 static const struct ws_panel_desc ws_panel_10_1_inch_a_4lane_desc = {
 	.init = ws_panel_10_1_a_4lane_init,
 	.mode = &ws_panel_10_1_a_mode,
@@ -1234,6 +2129,51 @@ static const struct ws_panel_desc ws_panel_10_1_inch_a_desc = {
 	.format = MIPI_DSI_FMT_RGB888,
 };
 
+static const struct ws_panel_desc ws_panel_10_1_inch_b_4lane_desc = {
+	.init = ws_panel_10_1_b_4lane_init,
+	.mode = &ws_panel_10_1_b_4lane_mode,
+	.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+		      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.lanes = 4,
+	.format = MIPI_DSI_FMT_RGB888,
+};
+
+static const struct ws_panel_desc ws_panel_10_1_inch_b_desc = {
+	.init = ws_panel_10_1_b_init,
+	.mode = &ws_panel_10_1_b_mode,
+	.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+		      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.lanes = 2,
+	.format = MIPI_DSI_FMT_RGB888,
+};
+
+static const struct ws_panel_desc ws_panel_9_inch_b_4lane_desc = {
+	.init = ws_panel_10_1_b_4lane_init,
+	.mode = &ws_panel_9_b_4lane_mode,
+	.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+		      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.lanes = 4,
+	.format = MIPI_DSI_FMT_RGB888,
+};
+
+static const struct ws_panel_desc ws_panel_9_inch_b_desc = {
+	.init = ws_panel_10_1_b_init,
+	.mode = &ws_panel_9_b_mode,
+	.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+		      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.lanes = 2,
+	.format = MIPI_DSI_FMT_RGB888,
+};
+
+static const struct ws_panel_desc ws_panel_8_8_inch_a_desc = {
+	.init = ws_panel_8_8_a_init,
+	.mode = &ws_panel_8_8_a_mode,
+	.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+		      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.lanes = 2,
+	.format = MIPI_DSI_FMT_RGB888,
+};
+
 static const struct ws_panel_desc ws_panel_8_inch_a_4lane_desc = {
 	.init = ws_panel_8_a_4lane_init,
 	.mode = &ws_panel_8_a_mode,
@@ -1279,11 +2219,40 @@ static const struct ws_panel_desc ws_panel_5_inch_a_desc = {
 	.format = MIPI_DSI_FMT_RGB888,
 };
 
+static const struct ws_panel_desc ws_panel_4_inch_c_desc = {
+	.init = ws_panel_4_c_init,
+	.mode = &ws_panel_4_c_mode,
+	.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+		      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.lanes = 2,
+	.format = MIPI_DSI_FMT_RGB888,
+};
+
+static const struct ws_panel_desc ws_panel_3_4_inch_c_desc = {
+	.init = ws_panel_3_4_c_init,
+	.mode = &ws_panel_3_4_c_mode,
+	.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+		      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+	.lanes = 2,
+	.format = MIPI_DSI_FMT_RGB888,
+};
+
 static const struct of_device_id ws_panel_of_match[] = {
+	{ .compatible = "waveshare,12.3-dsi-touch-a,4lane",
+	  &ws_panel_12_3_inch_a_4lane_desc },
 	{ .compatible = "waveshare,10.1-dsi-touch-a-4lane",
 	  &ws_panel_10_1_inch_a_4lane_desc },
 	{ .compatible = "waveshare,10.1-dsi-touch-a",
 	  &ws_panel_10_1_inch_a_desc },
+	{ .compatible = "waveshare,10.1-dsi-touch-b,4lane",
+	  &ws_panel_10_1_inch_b_4lane_desc },
+	{ .compatible = "waveshare,10.1-dsi-touch-b",
+	  &ws_panel_10_1_inch_b_desc },
+	{ .compatible = "waveshare,9.0-dsi-touch-b,4lane",
+	  &ws_panel_9_inch_b_4lane_desc },
+	{ .compatible = "waveshare,9.0-dsi-touch-b", &ws_panel_9_inch_b_desc },
+	{ .compatible = "waveshare,8.8-dsi-touch-a",
+	  &ws_panel_8_8_inch_a_desc },
 	{ .compatible = "waveshare,8.0-dsi-touch-a-4lane",
 	  &ws_panel_8_inch_a_4lane_desc },
 	{ .compatible = "waveshare,8.0-dsi-touch-a", &ws_panel_8_inch_a_desc },
@@ -1292,6 +2261,9 @@ static const struct of_device_id ws_panel_of_match[] = {
 	{ .compatible = "waveshare,5.5-dsi-touch-a",
 	  &ws_panel_5_5_inch_a_desc },
 	{ .compatible = "waveshare,5.0-dsi-touch-a", &ws_panel_5_inch_a_desc },
+	{ .compatible = "waveshare,4.0-dsi-touch-c", &ws_panel_4_inch_c_desc },
+	{ .compatible = "waveshare,3.4-dsi-touch-c",
+	  &ws_panel_3_4_inch_c_desc },
 	{}
 };
 MODULE_DEVICE_TABLE(of, ws_panel_of_match);
diff --git a/drivers/regulator/waveshare-panel-regulator.c b/drivers/regulator/waveshare-panel-regulator.c
index 158e8de3e117da..8b00b699b6105a 100644
--- a/drivers/regulator/waveshare-panel-regulator.c
+++ b/drivers/regulator/waveshare-panel-regulator.c
@@ -239,7 +239,7 @@ static int waveshare_panel_i2c_probe(struct i2c_client *i2c)
 			 data);
 
 	state->direction_state = 0;
-	state->poweron_state = BIT(9) | BIT(8) | BIT(4) | BIT(0); // Enable VCC
+	state->poweron_state = BIT(9) | BIT(8); // Enable VCC
 	regmap_write(regmap, REG_TP, state->poweron_state >> 8);
 	regmap_write(regmap, REG_LCD, state->poweron_state & 0xff);
 	msleep(20);