diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index 3a94ca211f9ce9..55ddd99fd7f6a8 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -346,6 +346,33 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_P030, .depth = 0, .num_planes = 2, .char_per_block = { 4, 8, 0 }, .block_w = { 3, 3, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true}, + { .format = DRM_FORMAT_S010, .depth = 0, .num_planes = 3, + .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, + .hsub = 2, .vsub = 2, .is_yuv = true}, + { .format = DRM_FORMAT_S210, .depth = 0, .num_planes = 3, + .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, + .hsub = 2, .vsub = 1, .is_yuv = true}, + { .format = DRM_FORMAT_S410, .depth = 0, .num_planes = 3, + .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, + .hsub = 1, .vsub = 1, .is_yuv = true}, + { .format = DRM_FORMAT_S012, .depth = 0, .num_planes = 3, + .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, + .hsub = 2, .vsub = 2, .is_yuv = true}, + { .format = DRM_FORMAT_S212, .depth = 0, .num_planes = 3, + .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, + .hsub = 2, .vsub = 1, .is_yuv = true}, + { .format = DRM_FORMAT_S412, .depth = 0, .num_planes = 3, + .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, + .hsub = 1, .vsub = 1, .is_yuv = true}, + { .format = DRM_FORMAT_S016, .depth = 0, .num_planes = 3, + .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, + .hsub = 2, .vsub = 2, .is_yuv = true}, + { .format = DRM_FORMAT_S216, .depth = 0, .num_planes = 3, + .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, + .hsub = 2, .vsub = 1, .is_yuv = true}, + { .format = DRM_FORMAT_S416, .depth = 0, .num_planes = 3, + .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, + .hsub = 1, .vsub = 1, .is_yuv = true}, }; unsigned int i; diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c index 675082a97bceb9..4eb9a63255fb12 100644 --- a/drivers/gpu/drm/vc4/vc4_plane.c +++ b/drivers/gpu/drm/vc4/vc4_plane.c @@ -36,6 +36,7 @@ static const struct hvs_format { u32 pixel_order; u32 pixel_order_hvs5; bool hvs5_only; + bool hvs6_only; } hvs_formats[] = { { .drm = DRM_FORMAT_XRGB8888, @@ -247,6 +248,42 @@ static const struct hvs_format { .pixel_order = HVS_PIXEL_ORDER_BGRA, .pixel_order_hvs5 = HVS_PIXEL_ORDER_RGBA, }, + { + .drm = DRM_FORMAT_P010, + .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_15_6_2PLANE, + .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR, + .hvs6_only = true, + }, + { + .drm = DRM_FORMAT_P012, + .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_15_6_2PLANE, + .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR, + .hvs6_only = true, + }, + { + .drm = DRM_FORMAT_P016, + .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_15_6_2PLANE, + .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR, + .hvs6_only = true, + }, + { + .drm = DRM_FORMAT_S010, + .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_9_0_3PLANE, + .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR, + .hvs6_only = true, + }, + { + .drm = DRM_FORMAT_S012, + .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_11_2_3PLANE, + .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR, + .hvs6_only = true, + }, + { + .drm = DRM_FORMAT_S016, + .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_15_6_3PLANE, + .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR, + .hvs6_only = true, + }, }; static const struct hvs_format *vc4_get_hvs_format(u32 drm_format) @@ -2635,6 +2672,12 @@ static bool vc4_format_mod_supported(struct drm_plane *plane, case DRM_FORMAT_YVU420: case DRM_FORMAT_NV16: case DRM_FORMAT_NV61: + case DRM_FORMAT_P010: + case DRM_FORMAT_P012: + case DRM_FORMAT_P016: + case DRM_FORMAT_S010: + case DRM_FORMAT_S012: + case DRM_FORMAT_S016: default: return (modifier == DRM_FORMAT_MOD_LINEAR); } @@ -2669,10 +2712,13 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev, }; for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) { - if (!hvs_formats[i].hvs5_only || vc4->gen >= VC4_GEN_5) { - formats[num_formats] = hvs_formats[i].drm; - num_formats++; - } + if (hvs_formats[i].hvs5_only && vc4->gen < VC4_GEN_5) + continue; + if (hvs_formats[i].hvs6_only && vc4->gen < VC4_GEN_6_C) + continue; + + formats[num_formats] = hvs_formats[i].drm; + num_formats++; } vc4_plane = drmm_universal_plane_alloc(dev, struct vc4_plane, base, diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h index 27158be19952c8..68d83d27c32ad9 100644 --- a/drivers/gpu/drm/vc4/vc4_regs.h +++ b/drivers/gpu/drm/vc4/vc4_regs.h @@ -1079,6 +1079,15 @@ enum hvs_pixel_format { HVS_PIXEL_FORMAT_AYUV444_RGB = 15, HVS_PIXEL_FORMAT_RGBA1010102 = 16, HVS_PIXEL_FORMAT_YCBCR_10BIT = 17, + /* 10 bit YUV420 formats with data with various different alignments */ + HVS_PIXEL_FORMAT_YCBCR_YUV420_15_6_2PLANE = 24, + HVS_PIXEL_FORMAT_YCBCR_YUV420_15_6_3PLANE = 25, + HVS_PIXEL_FORMAT_YCBCR_YUV420_13_4_2PLANE = 26, + HVS_PIXEL_FORMAT_YCBCR_YUV420_13_4_3PLANE = 27, + HVS_PIXEL_FORMAT_YCBCR_YUV420_11_2_2PLANE = 28, + HVS_PIXEL_FORMAT_YCBCR_YUV420_11_2_3PLANE = 29, + HVS_PIXEL_FORMAT_YCBCR_YUV420_9_0_2PLANE = 30, + HVS_PIXEL_FORMAT_YCBCR_YUV420_9_0_3PLANE = 31, }; /* Note: the LSB is the rightmost character shown. Only valid for diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 78abd819fd62e5..dffae521914842 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -377,6 +377,42 @@ extern "C" { */ #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') +/* + * 3 plane YCbCr LSB aligned + * In order to use these formats in a similar fashion to MSB aligned ones + * implementation can multiply the values by 2^6=64. For that reason the padding + * must only contain zeros. + * index 0 = Y plane, [15:0] z:Y [6:10] little endian + * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian + * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian + */ +#define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ +#define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ +#define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */ + +/* + * 3 plane YCbCr LSB aligned + * In order to use these formats in a similar fashion to MSB aligned ones + * implementation can multiply the values by 2^4=16. For that reason the padding + * must only contain zeros. + * index 0 = Y plane, [15:0] z:Y [4:12] little endian + * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian + * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian + */ +#define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ +#define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ +#define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */ + +/* + * 3 plane YCbCr + * index 0 = Y plane, [15:0] Y little endian + * index 1 = Cr plane, [15:0] Cr little endian + * index 2 = Cb plane, [15:0] Cb little endian + */ +#define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ +#define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ +#define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */ + /* * 3 plane YCbCr * index 0: Y plane, [7:0] Y