TL;DR
I added a battery voltage divider to a Pico 2 project and got readings nearly double the real battery voltage off the ADC pins. I spent a day ruling things out and ended up with what looks like undocumented A2 pad leakage. This is similar to #401, but while that report had IE enabled my issue persists with IE=0, verified by reading the pad register while the leak is active.
I've already ordered an A4 stepping board, so this issue is mostly just documentation in case this is truly novel and/or anyone else runs into a similar issue and is also confused!
This was found running a Raspberry Pi Pico 2 (chip marked RP2350A0A2, CHIP_ID.REVISION = 0x2), Pico SDK 2.2.0, battery-powered (VSYS = 3.08 V via external buck-boost; onboard RT6150 3V3 in regulation; ADC_VREF ≈ 3.3 V).
GPIO26 and GPIO27 (both tested independently) each source a small current that self-biases the pin to ~2.9–3.0 V whenever the pin is configured for ADC use per the datasheet (§12.4: digital input disabled, output disabled). This overpowers a high-impedance analog source: a 1 MΩ:1 MΩ battery divider that should put the pin at ~1.53 V instead reads ~2.9 V. The behavior matches the shape of erratum E9 but contradicts its documented conditions: E9 requires the pad input buffer enabled (IE=1) and parks at ~2.2 V; this leak persists with IE=0 (register-verified) and parks at ~3.0 V (~IOVDD − 0.3 V).
Pad state, dumped at runtime while the leak is active:
GP26 pad=0x00000092 ISO=0 OD=1 IE=0 PUE=0 PDE=0 funcsel=31 sio_oe=0 sio_out=0
GP27 pad=0x00000092 ISO=0 OD=1 IE=0 PUE=0 PDE=0 funcsel=31 sio_oe=0 sio_out=0
(adc_gpio_init() plus an explicit OD set; pulls disabled; pad ISO clear; FUNCSEL = NULL.)
I confirmed the current is real (not an ADC reading artifact): with a ~0.97MΩ resistor from the pin to GND and a ~0.97MΩ to the ~3.0 V battery rail, my DMM reads 3.0 V across the bottom resistor (~3.1 µA flowing) and ~0 V across the top one — i.e. the pin, not the battery, sources the current. With nothing attached but a 10 MΩ DMM, the bare pin reads ~3.05 V (≈0.3 µA). The two operating points imply the source current rises steeply as the pin voltage drops, consistent with the E9 curve's shape.
I ruled out the following via register dump and re-measurement:
- IE=1 (E9's documented condition) — leak persists with IE=0
- OD=0 — setting OD=1 changes nothing
- Pad ISO latching (condition 4 of E9) — ISO is 0 throughout
- Pulls — disabled
- ADC block enabled — leak persists with CS.EN=0 (I gate the ADC on only ~30 µs per 10 s)
- Latched state — driving the pin hard to GND via SIO for 1 ms clears it for <10 s, after which it re-establishes from voltage alone (observed via the divider recharging to ~2.9 V). 12-bit ADC raw counts (min/med/max of a 9-sample burst): 8/25/111 immediately after the pulse, back to ~3600 within 10 s.
I expected with IE=0 the pin should be high-impedance per the E9 text and the ADC input leakage spec (±1 µA max).
In #401 it was mentioned the team was still investigating. Is this within that scope? Should E9's conditions be broadened to note that on some A2 units the leakage persists or re-establishes with IE=0?
Happy to provide further testing and/or a simpler repro if y'all think it's worth pursuing!
TL;DR
I added a battery voltage divider to a Pico 2 project and got readings nearly double the real battery voltage off the ADC pins. I spent a day ruling things out and ended up with what looks like undocumented A2 pad leakage. This is similar to #401, but while that report had IE enabled my issue persists with IE=0, verified by reading the pad register while the leak is active.
I've already ordered an A4 stepping board, so this issue is mostly just documentation in case this is truly novel and/or anyone else runs into a similar issue and is also confused!
This was found running a Raspberry Pi Pico 2 (chip marked RP2350A0A2, CHIP_ID.REVISION = 0x2), Pico SDK 2.2.0, battery-powered (VSYS = 3.08 V via external buck-boost; onboard RT6150 3V3 in regulation; ADC_VREF ≈ 3.3 V).
GPIO26 and GPIO27 (both tested independently) each source a small current that self-biases the pin to ~2.9–3.0 V whenever the pin is configured for ADC use per the datasheet (§12.4: digital input disabled, output disabled). This overpowers a high-impedance analog source: a 1 MΩ:1 MΩ battery divider that should put the pin at ~1.53 V instead reads ~2.9 V. The behavior matches the shape of erratum E9 but contradicts its documented conditions: E9 requires the pad input buffer enabled (IE=1) and parks at ~2.2 V; this leak persists with IE=0 (register-verified) and parks at ~3.0 V (~IOVDD − 0.3 V).
Pad state, dumped at runtime while the leak is active:
GP26 pad=0x00000092 ISO=0 OD=1 IE=0 PUE=0 PDE=0 funcsel=31 sio_oe=0 sio_out=0
GP27 pad=0x00000092 ISO=0 OD=1 IE=0 PUE=0 PDE=0 funcsel=31 sio_oe=0 sio_out=0
(adc_gpio_init() plus an explicit OD set; pulls disabled; pad ISO clear; FUNCSEL = NULL.)
I confirmed the current is real (not an ADC reading artifact): with a ~0.97MΩ resistor from the pin to GND and a ~0.97MΩ to the ~3.0 V battery rail, my DMM reads 3.0 V across the bottom resistor (~3.1 µA flowing) and ~0 V across the top one — i.e. the pin, not the battery, sources the current. With nothing attached but a 10 MΩ DMM, the bare pin reads ~3.05 V (≈0.3 µA). The two operating points imply the source current rises steeply as the pin voltage drops, consistent with the E9 curve's shape.
I ruled out the following via register dump and re-measurement:
I expected with IE=0 the pin should be high-impedance per the E9 text and the ADC input leakage spec (±1 µA max).
In #401 it was mentioned the team was still investigating. Is this within that scope? Should E9's conditions be broadened to note that on some A2 units the leakage persists or re-establishes with IE=0?
Happy to provide further testing and/or a simpler repro if y'all think it's worth pursuing!