rvp: Fix shift amount masking in PSLL.DWS

Use 5-bit mask (0x1F) for shift amount instead of 8-bit field
extraction. Spec defines rs2[4:0] as shift amount. Also removes
incorrect >= 32 check that zeroed result.

Fixed instruction:
- PSLL.DWS: P-ext spec

Changed: P_FIELD(RS2, 0, 8) with >= 32 check  →  RS2 & 0x1F

Signed-off-by: Max Chou <max.chou@sifive.com>

Author: rnax

riscv/insns/psll_dws.h

@@ -1,7 +1,6 @@
 require_rv32;
 P_RD_RS1_DW_LOOP(32, 32, {
-  uint8_t m = P_FIELD(RS2, 0, 8);
+  uint8_t m = RS2 & 0x1F;
   const uint64_t maskN = 0xFFFFFFFFull;
-  if (m >= 32) p_rd = 0;
-  else p_rd = (uint32_t)((p_rs1 << m) & maskN);
+  p_rd = (uint32_t)((p_rs1 << m) & maskN);
 })