riscv-software-src · nibrunieAtSi5 · Jan 18, 2026
diff --git a/disasm/disasm.cc b/disasm/disasm.cc
@@ -1864,11 +1864,11 @@ void disassembler_t::add_instructions(const isa_parser_t* isa, bool strict)
     DISASM_OPIV_MULTIPLYADD__X__INSN(vwmaccus,  1);
     DISASM_OPIV_MULTIPLYADD_VX__INSN(vwmaccsu,  0);
 
-    if (ext_enabled(EXT_ZVQDOTQ)) {
-      DISASM_OPIV_VX__INSN(vqdot,   0);
-      DISASM_OPIV_VX__INSN(vqdotu,  0);
-      DISASM_OPIV_VX__INSN(vqdotsu, 0);
-      DISASM_OPIV__X__INSN(vqdotus, 0);
+    if (ext_enabled(EXT_ZVDOT4A8I)) {
+      DISASM_OPIV_VX__INSN(vdot4a, 0);
+      DISASM_OPIV_VX__INSN(vdot4au, 0);
+      DISASM_OPIV_VX__INSN(vdot4asu, 0);
+      DISASM_OPIV__X__INSN(vdot4aus, 0);
     }
 
     #undef DISASM_OPIV_VXI_INSN

diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc
@@ -302,8 +302,8 @@ void isa_parser_t::add_extension(const std::string& ext_str, const char* str)
     extension_table[EXT_ZVKSED] = true;
   } else if (ext_str == "zvksh") {
     extension_table[EXT_ZVKSH] = true;
-  } else if (ext_str == "zvqdotq") {
-    extension_table[EXT_ZVQDOTQ] = true;
+  } else if (ext_str == "zvdot4a8i") {
+    extension_table[EXT_ZVDOT4A8I] = true;
   } else if (ext_str == "zvqbdot8i") {
     extension_table[EXT_ZVQBDOT8I] = true;
   } else if (ext_str == "zvqbdot16i") {

diff --git a/riscv/encoding.h b/riscv/encoding.h
@@ -4,7 +4,7 @@
 
 /*
  * This file is auto-generated by running 'make' in
- * https://github.com/riscv/riscv-opcodes (4644ba3)
+ * https://github.com/riscv/riscv-opcodes (eb5c51c)
  */
 
 #ifndef RISCV_CSR_ENCODING_H
@@ -1725,6 +1725,20 @@
 #define MASK_VDIVU_VV 0xfc00707f
 #define MATCH_VDIVU_VX 0x80006057
 #define MASK_VDIVU_VX 0xfc00707f
+#define MATCH_VDOT4A_VV 0xb0002057
+#define MASK_VDOT4A_VV 0xfc00707f
+#define MATCH_VDOT4A_VX 0xb0006057
+#define MASK_VDOT4A_VX 0xfc00707f
+#define MATCH_VDOT4ASU_VV 0xa8002057
+#define MASK_VDOT4ASU_VV 0xfc00707f
+#define MATCH_VDOT4ASU_VX 0xa8006057
+#define MASK_VDOT4ASU_VX 0xfc00707f
+#define MATCH_VDOT4AU_VV 0xa0002057
+#define MASK_VDOT4AU_VV 0xfc00707f
+#define MATCH_VDOT4AU_VX 0xa0006057
+#define MASK_VDOT4AU_VX 0xfc00707f
+#define MATCH_VDOT4AUS_VX 0xb8006057
+#define MASK_VDOT4AUS_VX 0xfc00707f
 #define MATCH_VFADD_VF 0x5057
 #define MASK_VFADD_VF 0xfc00707f
 #define MATCH_VFADD_VV 0x1057
@@ -2233,20 +2247,6 @@
 #define MASK_VQBDOTS_VV 0xfc00707f
 #define MATCH_VQBDOTU_VV 0xb8000077
 #define MASK_VQBDOTU_VV 0xfc00707f
-#define MATCH_VQDOT_VV 0xb0002057
-#define MASK_VQDOT_VV 0xfc00707f
-#define MATCH_VQDOT_VX 0xb0006057
-#define MASK_VQDOT_VX 0xfc00707f
-#define MATCH_VQDOTSU_VV 0xa8002057
-#define MASK_VQDOTSU_VV 0xfc00707f
-#define MATCH_VQDOTSU_VX 0xa8006057
-#define MASK_VQDOTSU_VX 0xfc00707f
-#define MATCH_VQDOTU_VV 0xa0002057
-#define MASK_VQDOTU_VV 0xfc00707f
-#define MATCH_VQDOTU_VX 0xa0006057
-#define MASK_VQDOTU_VX 0xfc00707f
-#define MATCH_VQDOTUS_VX 0xb8006057
-#define MASK_VQDOTUS_VX 0xfc00707f
 #define MATCH_VQLDOTS_VV 0x9c000077
 #define MASK_VQLDOTS_VV 0xfc00707f
 #define MATCH_VQLDOTU_VV 0x98000077
@@ -3724,6 +3724,13 @@ DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV)
 DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX)
 DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV)
 DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX)
+DECLARE_INSN(vdot4a_vv, MATCH_VDOT4A_VV, MASK_VDOT4A_VV)
+DECLARE_INSN(vdot4a_vx, MATCH_VDOT4A_VX, MASK_VDOT4A_VX)
+DECLARE_INSN(vdot4asu_vv, MATCH_VDOT4ASU_VV, MASK_VDOT4ASU_VV)
+DECLARE_INSN(vdot4asu_vx, MATCH_VDOT4ASU_VX, MASK_VDOT4ASU_VX)
+DECLARE_INSN(vdot4au_vv, MATCH_VDOT4AU_VV, MASK_VDOT4AU_VV)
+DECLARE_INSN(vdot4au_vx, MATCH_VDOT4AU_VX, MASK_VDOT4AU_VX)
+DECLARE_INSN(vdot4aus_vx, MATCH_VDOT4AUS_VX, MASK_VDOT4AUS_VX)
 DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF)
 DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV)
 DECLARE_INSN(vfbdot_vv, MATCH_VFBDOT_VV, MASK_VFBDOT_VV)
@@ -3978,13 +3985,6 @@ DECLARE_INSN(vpaire_vv, MATCH_VPAIRE_VV, MASK_VPAIRE_VV)
 DECLARE_INSN(vpairo_vv, MATCH_VPAIRO_VV, MASK_VPAIRO_VV)
 DECLARE_INSN(vqbdots_vv, MATCH_VQBDOTS_VV, MASK_VQBDOTS_VV)
 DECLARE_INSN(vqbdotu_vv, MATCH_VQBDOTU_VV, MASK_VQBDOTU_VV)
-DECLARE_INSN(vqdot_vv, MATCH_VQDOT_VV, MASK_VQDOT_VV)
-DECLARE_INSN(vqdot_vx, MATCH_VQDOT_VX, MASK_VQDOT_VX)
-DECLARE_INSN(vqdotsu_vv, MATCH_VQDOTSU_VV, MASK_VQDOTSU_VV)
-DECLARE_INSN(vqdotsu_vx, MATCH_VQDOTSU_VX, MASK_VQDOTSU_VX)
-DECLARE_INSN(vqdotu_vv, MATCH_VQDOTU_VV, MASK_VQDOTU_VV)
-DECLARE_INSN(vqdotu_vx, MATCH_VQDOTU_VX, MASK_VQDOTU_VX)
-DECLARE_INSN(vqdotus_vx, MATCH_VQDOTUS_VX, MASK_VQDOTUS_VX)
 DECLARE_INSN(vqldots_vv, MATCH_VQLDOTS_VV, MASK_VQLDOTS_VV)
 DECLARE_INSN(vqldotu_vv, MATCH_VQLDOTU_VV, MASK_VQLDOTU_VV)
 DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS)

diff --git a/riscv/insns/vqdot_common.h → riscv/insns/vdot4a_common.h b/riscv/insns/vqdot_common.h → riscv/insns/vdot4a_common.h
@@ -5,7 +5,7 @@
     OUT_ARR[2] = (TYPE)((IN >> 16) & 0xff); \
     OUT_ARR[3] = (TYPE)((IN >> 24) & 0xff); \
 
-#define VQDOT(IN1, IN2, TYPE1, TYPE2) \
+#define VDOT4A(IN1, IN2, TYPE1, TYPE2) \
     UNPACK_32_TO_8(IN1, TYPE1, unpacked_vs1) \
     UNPACK_32_TO_8(IN2, TYPE2, unpacked_vs2) \
     uint64_t result = unpacked_vs1[0]*unpacked_vs2[0] + \

diff --git a/riscv/insns/vdot4a_vv.h b/riscv/insns/vdot4a_vv.h
@@ -0,0 +1,10 @@
+// vdot4a.vv vd, vs2, vs1, vm
+#include "vdot4a_common.h"
+
+require_extension(EXT_ZVDOT4A8I);
+require(P.VU.vsew == e32);
+
+VI_VV_LOOP({
+  VDOT4A(vs1, vs2, int8_t, int8_t);
+  vd = (vd + result) & 0xffffffff;
+})
diff --git a/riscv/insns/vdot4a_vx.h b/riscv/insns/vdot4a_vx.h
@@ -0,0 +1,10 @@
+// vdot4a.vx vd, vs2, rs1, vm
+#include "vdot4a_common.h"
+
+require_extension(EXT_ZVDOT4A8I);
+require(P.VU.vsew == e32);
+
+VI_VX_LOOP({
+  VDOT4A(rs1, vs2, int8_t, int8_t);
+  vd = (vd + result) & 0xffffffff;
+})
diff --git a/riscv/insns/vdot4asu_vv.h b/riscv/insns/vdot4asu_vv.h
@@ -0,0 +1,10 @@
+// vdot4asu.vv vd, vs2, vs1, vm
+#include "vdot4a_common.h"
+
+require_extension(EXT_ZVDOT4A8I);
+require(P.VU.vsew == e32);
+
+VI_VV_LOOP({
+  VDOT4A(vs1, vs2, uint8_t, int8_t);
+  vd = (vd + result) & 0xffffffff;
+})
diff --git a/riscv/insns/vdot4asu_vx.h b/riscv/insns/vdot4asu_vx.h
@@ -0,0 +1,10 @@
+// vdot4asu.vx vd, vs2, rs1, vm
+#include "vdot4a_common.h"
+
+require_extension(EXT_ZVDOT4A8I);
+require(P.VU.vsew == e32);
+
+VI_VX_LOOP({
+  VDOT4A(rs1, vs2, uint8_t, int8_t);
+  vd = (vd + result) & 0xffffffff;
+})
diff --git a/riscv/insns/vdot4au_vv.h b/riscv/insns/vdot4au_vv.h
@@ -0,0 +1,10 @@
+// vdot4au.vv vd, vs2, vs1, vm
+#include "vdot4a_common.h"
+
+require_extension(EXT_ZVDOT4A8I);
+require(P.VU.vsew == e32);
+
+VI_VV_LOOP({
+  VDOT4A(vs1, vs2, uint8_t, uint8_t);
+  vd = (vd + result) & 0xffffffff;
+})
diff --git a/riscv/insns/vdot4au_vx.h b/riscv/insns/vdot4au_vx.h
@@ -0,0 +1,10 @@
+// vdot4au.vx vd, vs2, rs1, vm
+#include "vdot4a_common.h"
+
+require_extension(EXT_ZVDOT4A8I);
+require(P.VU.vsew == e32);
+
+VI_VX_LOOP({
+  VDOT4A(rs1, vs2, uint8_t, uint8_t);
+  vd = (vd + result) & 0xffffffff;
+})
diff --git a/riscv/insns/vdot4aus_vx.h b/riscv/insns/vdot4aus_vx.h
@@ -0,0 +1,10 @@
+// vdot4aus.vx vd, vs2, rs1, vm
+#include "vdot4a_common.h"
+
+require_extension(EXT_ZVDOT4A8I);
+require(P.VU.vsew == e32);
+
+VI_VX_LOOP({
+  VDOT4A(rs1, vs2, int8_t, uint8_t);
+  vd = (vd + result) & 0xffffffff;
+})
diff --git a/riscv/insns/vqdot_vv.h b/riscv/insns/vqdot_vv.h
diff --git a/riscv/insns/vqdot_vx.h b/riscv/insns/vqdot_vx.h
diff --git a/riscv/insns/vqdotsu_vv.h b/riscv/insns/vqdotsu_vv.h
diff --git a/riscv/insns/vqdotsu_vx.h b/riscv/insns/vqdotsu_vx.h
diff --git a/riscv/insns/vqdotu_vv.h b/riscv/insns/vqdotu_vv.h
diff --git a/riscv/insns/vqdotu_vx.h b/riscv/insns/vqdotu_vx.h
diff --git a/riscv/insns/vqdotus_vx.h b/riscv/insns/vqdotus_vx.h
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h
@@ -78,7 +78,7 @@ typedef enum {
   EXT_ZVKNHB,
   EXT_ZVKSED,
   EXT_ZVKSH,
-  EXT_ZVQDOTQ,
+  EXT_ZVDOT4A8I,
   EXT_ZVQBDOT8I,
   EXT_ZVQBDOT16I,
   EXT_ZVFQBDOT8F,

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
@@ -867,21 +867,21 @@ riscv_insn_ext_v_ctrl = \
 	vsetvli \
 	vsetvl \
 
-riscv_insn_ext_zvqdotq = \
-	vqdot_vv \
-	vqdot_vx \
-	vqdotu_vv \
-	vqdotu_vx \
-	vqdotsu_vv \
-	vqdotsu_vx \
-	vqdotus_vx \
+riscv_insn_ext_zvdot4a8i = \
+	vdot4a_vv \
+	vdot4a_vx \
+	vdot4au_vv \
+	vdot4au_vx \
+	vdot4asu_vv \
+	vdot4asu_vx \
+	vdot4aus_vx \
 
 riscv_insn_ext_v = \
 	$(riscv_insn_ext_v_alu_fp) \
 	$(riscv_insn_ext_v_alu_int) \
 	$(riscv_insn_ext_v_ctrl) \
 	$(riscv_insn_ext_v_ldst) \
-	$(riscv_insn_ext_zvqdotq) \
+	$(riscv_insn_ext_zvdot4a8i) \
 
 riscv_insn_ext_h = \
 	hfence_gvma \