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riscv-software-src / riscv-isa-sim Public

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Fix rvp#2310

Merged

aswaterman merged 12 commits into

riscv-software-src:masterriscv-software-src/riscv-isa-sim:masterfrom

chihminchao:fix-rvpchihminchao/riscv-isa-sim:fix-rvpCopy head branch name to clipboard

Jul 10, 2026

Conversation Commits12 (12)Checks Files changed

Merged

Fix rvp#2310
aswaterman merged 12 commits into
riscv-software-src:masterfrom
chihminchao:fix-rvp

Commits

Commits on Jul 6, 2026

rvp: handle rv64 and rv32 overlap again
chihminchao
committed
rvp: fix shift w/ or w/o saturation
chihminchao
committed
rvp: fix the result extraction of multiplication
chihminchao
committed
rvp: do sext32 before writing to rd for rv32
chihminchao
committed
rvp: helper macro doesn't fit some nclip operation
chihminchao
committed
rvp: refine the sign-extension and extration of mulplication result
chihminchao
committed
rvp: fix and simplify behavior
chihminchao
committed
rvp: add missing vxsat updating
chihminchao
committed
rvp: Fix multiply-accumulate result extraction shift amount

rnax
authored and
chihminchao
committed
rvp: Fix packed multiply-subtract operation logic

rnax
authored and
chihminchao
committed
rvp: Fix shift amount masking in PSLL.DWS

rnax
authored and
chihminchao
committed
rvp: some rv32 multiplication instructions require extra sign-extension
chihminchao
committed

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