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Switch exception bits by correspond extensions#2324

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aswaterman merged 1 commit into
riscv-software-src:masterfrom
binno:enable_deleg_bit
Jun 25, 2026
Merged

Switch exception bits by correspond extensions#2324
aswaterman merged 1 commit into
riscv-software-src:masterfrom
binno:enable_deleg_bit

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@binno

@binno binno commented Jun 24, 2026

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if zicfi extension is enabled, software check fault existed.
if zicntr extension is enabled, hardware error fault existed.

Signed-off-by: Binno <binno.shen@sifive.com>
@aswaterman

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What bug is this fixing? I don't think Spike is doing anything wrong here.

@binno

binno commented Jun 25, 2026

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What bug is this fixing? I don't think Spike is doing anything wrong here.

I think this is not bug but more like the following operation:
If the Zca extension isn't enabled, misaligned fetch fault never happened
So the corresponding bit of medeleg is write ignored and mask out

bool medeleg_csr_t::unlogged_write(const reg_t val) noexcept {
  const reg_t mask = 0
    | (proc->extension_enabled(EXT_ZCA) ? 0 : 1 << CAUSE_MISALIGNED_FETCH)

@aswaterman aswaterman merged commit de0425a into riscv-software-src:master Jun 25, 2026
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2 participants