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Pull requests: riscv-software-src/riscv-isa-sim
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Add missing Ziccrse extension to disassembler fallback
#2330
opened Jun 25, 2026 by
mslijepc
Collaborator
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Switch exception bits by correspond extensions
#2324
opened Jun 24, 2026 by
binno
Contributor
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Report CBO.ZERO faults on effective address, not base address
#2297
opened May 15, 2026 by
aswaterman
Collaborator
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Raise illegal-instruction (not virtual) for indirect-CSR permission failures under V=1
#2290
opened May 8, 2026 by
jameshippisley
Contributor
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Fix execution when trigger/debug matched at interactive mode
#2269
opened Apr 7, 2026 by
Steven-Li-Xiaogang
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Fix incorrect mip.SEIP handling by adding hardware SEIP latch & correcting PLIC aliasing
#2218
opened Jan 21, 2026 by
rmkhurana28
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[Zvdot4a] Renaming Zvqdotq to Zvdot4a and vdotq to vdot4a
#2212
opened Jan 18, 2026 by
nibrunieAtSi5
Contributor
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Draft
Support RISC-V p-ext-proposal v0.9.12 for RV64
#2211
opened Jan 16, 2026 by
jason01180118
Contributor
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Support RISC-V p-ext-proposal v0.9.12 for RV32
#2210
opened Jan 16, 2026 by
jason01180118
Contributor
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Implemented the ability to execute any postprocess provided by the plugin after each instruction
#2172
opened Dec 2, 2025 by
kseniadobrovolskaya
Contributor
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Support label-based sideband commands for printing register contents
#2024
opened Jul 2, 2025 by
maerhart
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Updated in the last three days: updated:>2026-06-22.