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changing pdf links from relative and broken to absolute and scripted
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docs/spec/non-isa/abi.md

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title: ABI Specification
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id: abi
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hide_table_of_contents: true
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pdf: ../../../pdf/riscv-abi.pdf
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pdf: /pdf/riscv-abi.pdf
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Provides the processor-specific application binary interface document for RISC-V.

docs/spec/non-isa/advanced-interrupt.mdx

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title: Advanced Interrupt Architecture
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id: advanced-interrupt
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pdf: ../../../pdf/riscv-interrupts.pdf
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pdf: /pdf/riscv-interrupts.pdf
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Describes an Advanced Interrupt Architecture for RISC-V systems.

docs/spec/non-isa/debug-specification.md

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title: Debug Specification
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id: debug
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pdf: ../../../pdf/riscv-debug-specification.pdf
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pdf: /pdf/riscv-debug-specification.pdf
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Outlines a standard architecture for debug support on RISC-V hardware platforms. This architecture allows a variety of implementations and tradeoffs, which is complementary to the wide range of RISC-V implementations. At the same time, this specification defines common interfaces to allow debugging tools and components to target a variety of hardware platforms based on the RISC-V ISA.

docs/spec/non-isa/efficient-trace.md

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title: Efficient Trace
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id: efficient-trace
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pdf: ../../../pdf/riscv-trace-spec.pdf
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pdf: /pdf/riscv-trace-spec.pdf
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Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing.

docs/spec/non-isa/funtional-fixed-hardware.mdx

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title: Functional Fixed Hardware Specification
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id: functional-fixed
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pdf: ../../../pdf/riscv-ffh.pdf
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pdf: /pdf/riscv-ffh.pdf
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Provides additional system specification for RISC-V systems which use Advanced Configuration and Power Interface (ACPI), specifically for some ACPI object fields of type “Resource Descriptor”.

docs/spec/non-isa/io-mapping-table.mdx

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title: IO Mapping Table Specification
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id: io-mapping
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pdf: ../../../pdf/rimt-spec.pdf
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pdf: /pdf/rimt-spec.pdf
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Provides information about the RISC-V IOMMU and the relationship between the IO topology and the IOMMU in ACPI based RISC-V platforms. The RIMT identifies which components are behind IOMMU and how they are connected together.

docs/spec/non-isa/iommu-architecture.mdx

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title: IOMMU Architecture Specification
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id: iommu-architecture
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pdf: ../../../pdf/riscv-iommu.pdf
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pdf: /pdf/riscv-iommu.pdf
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Describes an Input-Output Memory Management Unit (IOMMU) that connects direct-memory-access-capable Input/Output (I/O) devices to system memory.

docs/spec/non-isa/n-trace.mdx

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title: N-Trace (Nexus-based Trace)
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id: n-trace
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pdf: ../../../pdf/RISC-V-N-Trace.pdf
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pdf: /pdf/RISC-V-N-Trace.pdf
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Implements the IEEE-5001 Nexus Standard tailored to support the trace of RISC-V ISA cores, harts and SoC/MCU designs.

docs/spec/non-isa/platform-level-interrupt-controller.mdx

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title: Platform-Level Interrupt Controller Specification
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id: platform-interrupt
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pdf: ../../../pdf/riscv-plic-1.0.0.pdf
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pdf: /pdf/riscv-plic-1.0.0.pdf
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Delineates the operational parameters for a platform-level interrupt controller on RISC-V.

docs/spec/non-isa/qos-interface.md

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description: ~60 character description
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id: qos
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pdf: ../../../pdf/riscv-cbqri.pdf
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pdf: /pdf/riscv-cbqri.pdf
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Specifies:

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