rockchip64: rk3528: fix ethernet PHY detection on NanoPi Zero2 (6.18 + 7.0)

Fix ethernet PHY not being detected on the NanoPi Zero2. The MDIO bus
scan was failing because the PHY reset GPIO was only defined on the
PHY child node inside the MDIO bus. The kernel processes this reset
after the MDIO scan, but the PHY needs reset released before it will
respond on the bus.

Move the reset control to the gmac1 node using snps,reset-gpios and
snps,reset-delays-us properties. The stmmac driver handles these
during MDIO bus registration, before scanning for PHY devices.

Also change CONFIG_MOTORCOMM_PHY from module (m) to built-in (y) in
the rockchip64 kernel config. As a module, the PHY driver loads too
late for the MDIO bus scan to find the PHY during boot.

Tested on hardware: ethernet link at 1000Mbps full duplex confirmed.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

Author: rubycomm

config/kernel/linux-rockchip64-current.config

@@ -906,7 +906,7 @@ CONFIG_MARVELL_88X2222_PHY=m
 CONFIG_MAXLINEAR_GPHY=m
 CONFIG_MICREL_PHY=y
 CONFIG_MICROCHIP_T1_PHY=m
-CONFIG_MOTORCOMM_PHY=m
+CONFIG_MOTORCOMM_PHY=y
 CONFIG_NATIONAL_PHY=m
 CONFIG_NXP_C45_TJA11XX_PHY=m
 CONFIG_AT803X_PHY=m

patch/kernel/archive/rockchip64-6.18/rk3528-14-arm64-dts-rockchip-nanopi-zero2-fix-ethernet-phy-reset.patch

@@ -0,0 +1,48 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Shlomi Marco <s.marco@rubycomm.com>
+Date: Wed, 26 Mar 2026 00:00:00 +0000
+Subject: arm64: dts: rockchip: nanopi-zero2: fix ethernet PHY reset
+
+Move the Ethernet PHY reset control from the MDIO bus PHY node to the
+GMAC controller node using the SNPS reset properties (snps,reset-gpios
+and snps,reset-delays-us). This ensures the PHY is properly reset by
+the GMAC driver during initialization, which is required for reliable
+link establishment on the NanoPi Zero2.
+
+The per-PHY reset-gpios, reset-assert-us, reset-deassert-us, and their
+associated pinctrl properties in the MDIO PHY node are removed, as they
+are not handled by the generic PHY framework for RGMII PHYs.
+
+Signed-off-by: Shlomi Marco <s.marco@rubycomm.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts
+@@ -217,6 +217,8 @@
+ 	pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>,
+ 		    <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>;
+ 	status = "okay";
++	snps,reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
++	snps,reset-delays-us = <0 20000 100000>;
+ };
+
+ &gpu {
+@@ -244,12 +246,7 @@
+ &mdio1 {
+ 	rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+ 		reg = <0x1>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&gmac1_rstn_l>;
+-		reset-assert-us = <20000>;
+-		reset-deassert-us = <100000>;
+-		reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+ 	};
+ };
+
+-- 
+Armbian

patch/kernel/archive/rockchip64-7.0/rk3528-14-arm64-dts-rockchip-nanopi-zero2-fix-ethernet-phy-reset.patch

@@ -0,0 +1,48 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Shlomi Marco <s.marco@rubycomm.com>
+Date: Wed, 26 Mar 2026 00:00:00 +0000
+Subject: arm64: dts: rockchip: nanopi-zero2: fix ethernet PHY reset
+
+Move the Ethernet PHY reset control from the MDIO bus PHY node to the
+GMAC controller node using the SNPS reset properties (snps,reset-gpios
+and snps,reset-delays-us). This ensures the PHY is properly reset by
+the GMAC driver during initialization, which is required for reliable
+link establishment on the NanoPi Zero2.
+
+The per-PHY reset-gpios, reset-assert-us, reset-deassert-us, and their
+associated pinctrl properties in the MDIO PHY node are removed, as they
+are not handled by the generic PHY framework for RGMII PHYs.
+
+Signed-off-by: Shlomi Marco <s.marco@rubycomm.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts
+@@ -217,6 +217,8 @@
+ 	pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>,
+ 		    <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>;
+ 	status = "okay";
++	snps,reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
++	snps,reset-delays-us = <0 20000 100000>;
+ };
+
+ &gpu {
+@@ -244,12 +246,7 @@
+ &mdio1 {
+ 	rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+ 		reg = <0x1>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&gmac1_rstn_l>;
+-		reset-assert-us = <20000>;
+-		reset-deassert-us = <100000>;
+-		reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+ 	};
+ };
+
+-- 
+Armbian