PPC64: P10 prefixed-load fast paths for loadPtr/loadDouble/loadFloat32/loadUnalignedSimd128 (Address)

Adds a HasPOWER10()+34-bit-signed-offset fast path before the
movePtr+indexed-load fallback in:
- loadPtr(Address) → as_pld
- loadDouble(Address) → as_plfd
- loadFloat32(Address) → as_plfs
- loadUnalignedSimd128(Address) → as_plxv

Each replaces the 2-insn `movePtr scratch + lXdx` sequence (plus a
GPR scratch acquire) with a single 8-byte prefixed load when the
offset fits 34-bit signed. Hot on deep stack frames where slot
offsets exceed 16-bit signed (loadPtr) and on FP/SIMD reads from
constant-offset structure fields. The DS-form (loadPtr) and 16-bit-
signed (loadDouble/Float32) fast paths are still preferred when
applicable — they're 4 bytes vs 8 for the prefixed form.

All four emitters (`as_pld` / `as_plfd` / `as_plfs` / `as_plxv`)
were already wired and used elsewhere; this commit only plumbs them
into the Address-form load helpers.

Verified across the verification matrix:
- Real-P9 (`obj-sm-dbgopt`): wasm/large-memory + wasm/memory +
  wasm/spec/spec/address + ion + basic 3958/0
- Real-P10 (`power10`): same suite 3958/0
- ARM64 sim FORCE_POWER10: same suite 3958/0

Closes PLAN.md candidates mozilla-firefox#19 (read-side), mozilla-firefox#29, mozilla-firefox#30. Item mozilla-firefox#31
(prefixed-store side) still pending — it needs new emitters
(as_pstd/as_pstfd/as_pstfs/as_pstxv) and matching sim decoders.

Author: runlevel5

js/src/jit/ppc64/MacroAssembler-ppc64-inl.h

@@ -3315,6 +3315,12 @@ inline void MacroAssembler::cmp32Set(Assembler::Condition cond, Address lhs,
 FaultingCodeOffset MacroAssembler::loadUnalignedSimd128(const Address& src,
                                                         FloatRegister dest) {
   UseScratchRegisterScope temps(asMasm());
+  if (HasPOWER10() && is_intN((intptr_t)src.offset, 34)) {
+    // POWER10 prefixed load — natural-LE byte order, no GPR scratch.
+    return FaultingCodeOffset(
+        as_plxv(dest.encoding(), src.base, (int64_t)src.offset, /*R=*/false)
+            .getOffset());
+  }
   if (HasPOWER9()) {
     // POWER9: lxvx (X-form, indexed) loads 128 bits in correct LE order.
     Register scratch = temps.Acquire();

js/src/jit/ppc64/MacroAssembler-ppc64.h

@@ -1439,6 +1439,11 @@ class MacroAssemblerPPC64Compat : public MacroAssemblerPPC64 {
       return FaultingCodeOffset(
           as_ld(dest, address.base, address.offset).getOffset());
     }
+    if (HasPOWER10() && is_intN((intptr_t)address.offset, 34)) {
+      return FaultingCodeOffset(
+          as_pld(dest, address.base, (int64_t)address.offset, /*R=*/false)
+              .getOffset());
+    }
     UseScratchRegisterScope temps(*this);
     Register scratch = temps.Acquire();
     MOZ_ASSERT(scratch != dest);
@@ -1474,6 +1479,11 @@ class MacroAssemblerPPC64Compat : public MacroAssemblerPPC64 {
       return FaultingCodeOffset(
           as_lfd(dest, addr.base, addr.offset).getOffset());
     }
+    if (HasPOWER10() && is_intN((intptr_t)addr.offset, 34)) {
+      return FaultingCodeOffset(
+          as_plfd(dest, addr.base, (int64_t)addr.offset, /*R=*/false)
+              .getOffset());
+    }
     UseScratchRegisterScope temps(*this);
     Register scratch = temps.Acquire();
     movePtr(ImmWord(addr.offset), scratch);
@@ -1495,6 +1505,11 @@ class MacroAssemblerPPC64Compat : public MacroAssemblerPPC64 {
       return FaultingCodeOffset(
           as_lfs(dest, addr.base, addr.offset).getOffset());
     }
+    if (HasPOWER10() && is_intN((intptr_t)addr.offset, 34)) {
+      return FaultingCodeOffset(
+          as_plfs(dest, addr.base, (int64_t)addr.offset, /*R=*/false)
+              .getOffset());
+    }
     UseScratchRegisterScope temps(*this);
     Register scratch = temps.Acquire();
     movePtr(ImmWord(addr.offset), scratch);