debug: add PW_block_0_Cout5 single-kernel test for integration bug

New test matching the integrated blocks.0.pw first-tile shape
(C_in=8, C_out=5, HW=48×48) to isolate whether the 40% dW[0] drift
in integrated MobileNet is a kernel-level bug or integration bug.

Result: standalone test passes bit-exact (2/40 err at FP32 noise
level 1e-6 rel). Kernel itself works correctly. Bug is
integration-specific.

Author: runwangdl

debug/gen_kernel_tests.py

@@ -423,6 +423,9 @@ def build_gradw_generic(out_dir: Path, Ci: int, Co: int, Hi: int, Wi: int,
     # block_0 PW 8→16 HW=48 (biggest PW shape in MobileNet — most stressful for L1)
     ("PW_block_0",    "X",   8,  16,  48,  48,  48, 48, 1, 1, 1, 0,   1),
     ("PW_block_0",    "W",   8,  16,  48,  48,  48, 48, 1, 1, 1, 0,   1),
+    # blocks.0.pw integrated C_out tile shape — reproduces integration-only bug
+    # where C_out=5 < NUM_CORES=8 produces ~40% off dW[0]
+    ("PW_block_0_Cout5","W",  8,   5,  48,  48,  48, 48, 1, 1, 1, 0,   1),
     # block_1 DW stride-2 (C=16 HW 48→24)
     ("DW_block_1_s2", "X",  16,  16,  48,  48,  24, 24, 3, 3, 2, 1,  16),
     ("DW_block_1_s2", "W",  16,  16,  48,  48,  24, 24, 3, 3, 2, 1,  16),