Merge pull request #163 from thejpster/release-prep

Release prep

Author: jonathanpallant

aarch32-cpu/CHANGELOG.md

@@ -7,10 +7,33 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [aarch32-cpu v0.3.0]
+
+### Added
+
 - Added `Iciallu` register which allows invalidating the instruction cache.
+- Added `asm::fiq_enable` and `asm::fiq_disable`
+- Added `stacks::stack_used_bytes` to count how much stack has been used
+- Added `svc1!`-`svc6!` macros for making syscalls
+- Added `hvc!` and `hvc1!`-`hvc6!` macros for making hypercalls
+- Added `mmu::L1Table` type for basic MMU L1 page-tables
+- Added `Prlar::limit_address` method
+- Added `Prbar::base_address` method
 - `register::vbar` and `register::Vbar` are also available for ARMv7-A now.
 - Added `defmt` implementations for PMSA types.
 
+### Changed
+
+- Updated `bitbybit` crate to version 2
+- Updated `SysRegRead::read_raw` and `SysRegRead64::read_raw` to now be safe operations
+- Updated `Dfsr` datatype to support a range of Arm architecture versions
+- Updated Arm Generic Timer support - now works on Armv7-A as well
+- Updated Hypervisor support - now works on Armv7-A as well
+
+### Removed
+
+- Removed `__sync_synchronize` function
+
 ## [aarch32-cpu v0.2.0]
 
 - Mark `asm::irq_enable()` as unsafe to match `interrupt::enable()`
@@ -70,7 +93,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 Initial release
 
-[Unreleased]: https://github.com/rust-embedded/aarch32/compare/aarch32-cpu-v0.2.0...HEAD
+[Unreleased]: https://github.com/rust-embedded/aarch32/compare/aarch32-cpu-v0.3.0...HEAD
+[aarch32-cpu v0.3.0]: https://github.com/rust-embedded/aarch32/compare/aarch32-cpu-v0.2.0...aarch32-cpu-v0.3.0
 [aarch32-cpu v0.2.0]: https://github.com/rust-embedded/aarch32/compare/aarch32-cpu-v0.1.0...aarch32-cpu-v0.2.0
 [aarch32-cpu v0.1.0]: https://github.com/rust-embedded/aarch32/compare/cortex-ar-v0.3.0...aarch32-cpu-v0.1.0
 [cortex-ar v0.3.0]: https://github.com/rust-embedded/aarch32/compare/cortex-ar-v0.2.0...cortex-ar-v0.3.0

aarch32-cpu/Cargo.toml

@@ -22,7 +22,7 @@ readme = "README.md"
 repository = "https://github.com/rust-embedded/aarch32.git"
 homepage = "https://github.com/rust-embedded/aarch32"
 rust-version = "1.83"
-version = "0.2.0"
+version = "0.3.0"
 
 [dependencies]
 arbitrary-int = "2"

aarch32-rt-macros/CHANGELOG.md

@@ -10,8 +10,12 @@ As of *aarch32-rt-macros v0.1.0*, this project is released in lock-step with
 
 ## [Unreleased]
 
+## [aarch32-rt-macros v0.3.0]
+
 - Handle outer `unsafe` for whitelisted proc macro attributes. For example, this allows
   `#[unsafe(link_section="...")]` which previously did not work.
+- Added support for `HypervisorCall` exception
+- Changed `SupervisorCall` handler to add `&Frame` parameter, and keep original code as inner function
 
 ## [aarch32-rt-macros v0.2.0]
 
@@ -29,7 +33,8 @@ As of *aarch32-rt-macros v0.1.0*, this project is released in lock-step with
 
 Initial release
 
-[Unreleased]: https://github.com/rust-embedded/aarch32/compare/aarch32-rt-v0.2.0...HEAD
+[Unreleased]: https://github.com/rust-embedded/aarch32/compare/aarch32-rt-v0.3.0...HEAD
+[aarch32-rt-macros v0.3.0]: https://github.com/rust-embedded/aarch32/compare/aarch32-rt-v0.2.0...aarch32-rt-v0.3.0
 [aarch32-rt-macros v0.2.0]: https://github.com/rust-embedded/aarch32/compare/aarch32-rt-v0.1.0...aarch32-rt-v0.2.0
 [aarch32-rt-macros v0.1.0]: https://github.com/rust-embedded/aarch32/compare/cortex-ar-rt-macros-v0.1.1...aarch32-rt-v0.1.0
 [cortex-ar-rt-macros v0.1.1]: https://github.com/rust-embedded/aarch32/compare/cortex-ar-rt-macros-v0.1.0...cortex-ar-rt-macros-v0.1.1

aarch32-rt-macros/Cargo.toml

@@ -12,7 +12,7 @@ readme = "README.md"
 repository = "https://github.com/rust-embedded/aarch32.git"
 homepage = "https://github.com/rust-embedded/aarch32"
 rust-version = "1.83"
-version = "0.2.0"
+version = "0.3.0"
 
 [lib]
 proc-macro = true

aarch32-rt/CHANGELOG.md

@@ -7,6 +7,25 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [aarch32-rt v0.3.0]
+
+### Added
+
+- `el2-mode` feature, to keep CPU in EL2 mode
+- Discard entry for `.ARM.exidx` and `.ARM.extab` sections
+- Region alignment support, with `_region_alignment` linker symbol
+- `__sXXX` and `__eXXX` linker symbols for each output section
+- Support for setting up stacks for multiple cores
+- Support for exception handling at EL2 (including a new `HypervisorCall` handler)
+- `.pushsection` and `.popsection` to all assembly blocks to avoid accidentally changing the section of another piece of code
+- New `sections` module for getting information about linker output sections at run-time
+
+### Changed
+
+- Default stack size now 16K, except FIQ and IRQ which are 64 bytes
+- `SupervisorCall` now gets a `&Frame` argument
+- `_init_segments` function now zeroes out the stack space
+
 ## [aarch32-rt v0.2.0]
 
 ### Changed
@@ -59,7 +78,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 Initial release
 
-[Unreleased]: https://github.com/rust-embedded/aarch32/compare/aarch32-rt-v0.2.0...HEAD
+[Unreleased]: https://github.com/rust-embedded/aarch32/compare/aarch32-rt-v0.3.0...HEAD
+[aarch32-rt v0.3.0]: https://github.com/rust-embedded/aarch32/compare/aarch32-rt-v0.2.0...aarch32-rt-v0.3.0
 [aarch32-rt v0.2.0]: https://github.com/rust-embedded/aarch32/compare/aarch32-rt-v0.1.0...aarch32-rt-v0.2.0
 [aarch32-rt v0.1.0]: https://github.com/rust-embedded/aarch32/compare/cortex-r-rt-v0.2.1...aarch32-rt-v0.1.0
 [cortex-r-rt v0.2.1]: https://github.com/rust-embedded/aarch32/compare/cortex-r-rt-v0.2.0...cortex-r-rt-v0.2.1

aarch32-rt/Cargo.toml

@@ -21,11 +21,11 @@ name = "aarch32-rt"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/aarch32.git"
 rust-version = "1.83"
-version = "0.2.0"
+version = "0.3.0"
 
 [dependencies]
-aarch32-cpu = { version = "0.2.0", path = "../aarch32-cpu" }
-aarch32-rt-macros = { path = "../aarch32-rt-macros", version = "=0.2.0" }
+aarch32-cpu = { version = "0.3.0", path = "../aarch32-cpu" }
+aarch32-rt-macros = { path = "../aarch32-rt-macros", version = "=0.3.0" }
 
 [features]
 # Enable the FPU on start-up, even on a soft-float EABI target

arm-targets/CHANGELOG.md

@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.4.2]
+
 ### Changed
 
 - Take `CARGO_CFG_TARGET_*` variables into account for detecting targets.
@@ -57,7 +59,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 Initial release
 
-[Unreleased]: https://github.com/rust-embedded/aarch32/compare/arm-targets-v0.4.0...HEAD
+[Unreleased]: https://github.com/rust-embedded/aarch32/compare/arm-targets-v0.4.2...HEAD
+[v0.4.2]: https://github.com/rust-embedded/aarch32/compare/arm-targets-v0.4.1...arm-targets-v0.4.2
+[v0.4.1]: https://github.com/rust-embedded/aarch32/compare/arm-targets-v0.4.0...arm-targets-v0.4.1
 [v0.4.0]: https://github.com/rust-embedded/aarch32/compare/arm-targets-v0.3.0...arm-targets-v0.4.0
 [v0.3.0]: https://github.com/rust-embedded/aarch32/compare/arm-targets-v0.2.0...arm-targets-v0.3.0
 [v0.2.0]: https://github.com/rust-embedded/aarch32/compare/arm-targets-v0.1.0...arm-targets-v0.2.0

examples/versatileab/Cargo.toml

@@ -20,7 +20,7 @@ aarch32-rt = { path = "../../aarch32-rt" }
 arbitrary-int = "2.1.1"
 derive-mmio = "0.6.1"
 libm = "0.2.15"
-pl190-vic = "0.1.1"
+pl190-vic = "0.1.2"
 portable-atomic = { version = "1.11.1", features = ["critical-section"] }
 semihosting = { version = "0.1.18", features = ["stdio"] }
 
@@ -30,6 +30,3 @@ arm-targets = { version = "0.4.0", path = "../../arm-targets" }
 [features]
 eabi-fpu = ["aarch32-rt/eabi-fpu"]
 fpu-d32 = ["aarch32-rt/fpu-d32"]
-
-[patch.crates-io]
-aarch32-cpu = { path = "../../aarch32-cpu" }