Add dual-core Cortex-A examples

[jonathanpallant]

The AMD Zynq 7000:

• is emulated by QEMU
• is popular with users of this crate
• has two Cortex-A9 cores, so can test SMP support on Cortex-A (we only test dual-core Cortex-R52 currently)
• has a PMSAv7 MMU, so we can test that code too

So a simple Zynq 7000 example in this tree might be useful.

[sriramster]

Hello @jonathanpallant I wanted to take this issue up. But I've a few questions would you help?

• The arm_gic currently won't support GICv1, zynx-7000 uses this.
• The timers that current code base supports are virtual, physical on EL*, A9 have a different mechanism for this. Do you recommend on extending the Timer framework to support Physical, Private and Watchdog?

Thank you.

[jonathanpallant]

1. So we'll need a GICv1 driver (@robamu what do you use?)
2. Can the Cortex-A9 timers meet the trait I added? If so I guess we can move it into a timer module and have cfg-gated modules for the implementations on different architectures.

[sriramster]

Yes, for (2) Adding/Extending the generic_timer module from the trait would suffice. And the invocation could be cfg-gated. I'll wait for (1). From @robamu . Thank you.

[robamu]

I have a low level PAC API which is part of the zynq7000 crate and a more high level driver in zynq7000-hal. Those might help.

GIC PAC: https://github.com/us-irs/zynq7000-rs/blob/main/firmware%2Fzynq7000%2Fsrc%2Fgic.rs
GIC HAL: https://github.com/us-irs/zynq7000-rs/blob/main/firmware%2Fzynq7000-hal%2Fsrc%2Fgic.rs

[robamu]

I was planning a new HAL release.. but another option would also be to copy and paste relevant stuff and API, or combine the approached and only use the PAC, write a very basic HAL driver for the example.

[sriramster]

@robamu Do you recommend having just the driver code within the examples? (In this case for the specific example)