arm-targets v0.4.2

• Take CARGO_CFG_TARGET_* variables into account for detecting targets.

aarch32-rt v0.3.0

• el2-mode feature, to keep CPU in EL2 mode
• Discard entry for .ARM.exidx and .ARM.extab sections
• Region alignment support, with _region_alignment linker symbol
• __sXXX and __eXXX linker symbols for each output section
• Support for setting up stacks for multiple cores
• Support for exception handling at EL2 (including a new HypervisorCall handler)
• .pushsection and .popsection to all assembly blocks to avoid accidentally changing the section of another piece of code
• New sections module for getting information about linker output sections at run-time

aarch32-cpu v0.3.0

• Added Iciallu register which allows invalidating the instruction cache.
• Added asm::fiq_enable and asm::fiq_disable
• Added stacks::stack_used_bytes to count how much stack has been used
• Added svc1!-svc6! macros for making syscalls
• Added hvc! and hvc1!-hvc6! macros for making hypercalls
• Added mmu::L1Table type for basic MMU L1 page-tables
• Added Prlar::limit_address method
• Added Prbar::base_address method
• register::vbar and register::Vbar are also available for ARMv7-A now.
• Added defmt implementations for PMSA types.

aarch32-rt v0.2.0

What's Changed

• Reworked stack allocation by @umohr-irs in #93
  • NOTE: You will need to add a STACKS alias to your memory.x file
• Change the entry macro to properly hide the main function. by @jonathanpallant in #102

New Contributors

• @umohr-irs made their first contribution in #93

Full Changelog: aarch32-rt-v0.1.0...aarch32-rt-v0.2.0

aarch32-cpu v0.2.0

What's Changed

• docs: fix aarch32-cpu link in README by @nyurik in #91
• Mark asm::irq_enable as unsafe by @jonathanpallant in #104

New Contributors

• @nyurik made their first contribution in #91

Full Changelog: aarch32-cpu-v0.1.0...aarch32-cpu-v0.2.0

arm-targets v0.4.0

Added

• Added Arch::Armv6

Changed

• Targets starting with thumb are identified as T32 targets

aarch32-rt v0.1.0

First release of the new aarch32-rt crate. This crate replaces both cortex-r-rt and cortex-a-rt.

Added

• ARMv7-A support, by merging with the old cortex-a-rt crate
• ARMv4T and ARMv5TE support
• Thumb mode target support
• fpu-d32 feature (was called vfp-dp in the old cortex-a-rt)

Changed

• Renamed from cortex-r-rt to aarch32-rt
• Restarted numbering from 0.1.0
• Fixed SVC handling from T32 mode

aarch32-cpu v0.1.0

First release of aarch32-cpu. This replaces cortex-ar.

Added

• ARMv4T and ARMv5TE support
• Thumb mode target support

Changed

• Renamed from cortex-ar to aarch32-cpu
• Restarted numbering from 0.1.0
• All BAR register types now hold plain u32, not *mut u32 - fixes issues with serde derives on some types

cortex-a-rt v0.1.1

Patch release to fix documentation build on docs.rs.

cortex-r-rt v0.2.0

Added

• Added ABT und UND mode stack setup.
• Default exception handlers for undefined, prefetch abort and data abort exceptions
• SMP support
• Zeroing of registers on start-up
• #[entry] and #[exception] and #[interrupt] macros

Changed

• Fixed interrupt handler so interrupts can be re-entrant
• Default Rust exception handler is now an empty permanent loop instead of a semihosting exit.
• The SVC asm trampoline can now be over-ridden
• The Undefined, Prefetch and Abort handlers can either return never, or can return a new address to continue executing from when the handler is over