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Add TLBI (TLB Invalidate) instruction wrappers
Add safe wrappers for AArch64 TLBI system instructions at EL1, following the existing pattern established by barrier.rs. Covered instructions: - VMALLE1 / VMALLE1IS — invalidate all EL1&0 TLB entries - VAE1 / VAE1IS — invalidate by VA (with ASID) - VALE1 / VALE1IS — invalidate by VA, last level only - VAAE1 / VAAE1IS — invalidate by VA, all ASIDs - VAALE1 / VAALE1IS — invalidate by VA, all ASIDs, last level - ASIDE1 / ASIDE1IS — invalidate by ASID Each wrapper includes documentation with operand encoding details per Arm ARM §C5.5 / §D8.10. Signed-off-by: ZhiHong Niu <z.h.niu@outlook.com> Signed-off-by: Niu Zhihong <zhihong@nzhnb.com>
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‎src/asm.rs‎

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pub mod barrier;
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pub mod random;
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pub mod tlbi;
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/// The classic no-op
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#[inline(always)]

‎src/asm/tlbi.rs‎

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// SPDX-License-Identifier: Apache-2.0 OR MIT
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//
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// Copyright (c) 2018-2026 by the author(s)
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//
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// Author(s):
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// - ZhiHong Niu <zhihong@nzhnb.com>
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//! TLB Invalidate (TLBI) instructions.
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//!
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//! Provides Rust wrappers around AArch64 TLBI system instructions for
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//! invalidating TLB entries at EL1.
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//!
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//! # Operand Encoding
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//!
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//! For address-based TLBI operations (`vae1`, `vale1`, `vaae1`, `vaale1`),
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//! the `u64` operand is encoded as specified in the Arm ARM:
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//!
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//! - Bits \[55:48\]: ASID (for non-"AA" variants)
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//! - Bits \[43:0\]: VA\[55:12\] (the virtual address shifted right by 12)
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//!
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//! It is the caller's responsibility to construct the operand correctly.
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//!
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//! # Synchronization
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//!
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//! TLBI instructions must be surrounded by appropriate barrier instructions
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//! (DSB before and DSB+ISB after) to ensure the invalidation takes effect.
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//! See [`barrier`](super::barrier).
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//!
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//! # References
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//!
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//! - [Arm ARM §C5.5 - A64 system instructions for TLB maintenance](https://developer.arm.com/documentation/ddi0487/latest)
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//! - [Arm ARM §D8.10 - TLB maintenance instructions](https://developer.arm.com/documentation/ddi0487/latest)
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//!
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//! # Example
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//!
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//! ```no_run
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//! use aarch64_cpu::asm::{barrier, tlbi};
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//!
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//! // Invalidate all EL1&0 regime TLB entries.
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//! // A DSB before ensures prior stores to page tables are visible;
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//! // a DSB+ISB after ensures the invalidation completes before
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//! // subsequent memory accesses.
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//! barrier::dsb(barrier::SY);
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//! tlbi::vmalle1();
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//! barrier::dsb(barrier::SY);
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//! barrier::isb(barrier::SY);
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//!
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//! // Invalidate by VA: encode operand as VA[55:12] | (ASID << 48).
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//! let vaddr: u64 = 0x8000_0000;
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//! let asid: u64 = 1;
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//! let operand = (vaddr >> 12) | (asid << 48);
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//! barrier::dsb(barrier::SY);
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//! tlbi::vae1(operand);
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//! barrier::dsb(barrier::SY);
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//! barrier::isb(barrier::SY);
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//! ```
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/// Invalidate all EL1&0 regime TLB entries in the current VMID.
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///
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/// Executes `TLBI VMALLE1`.
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#[inline(always)]
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pub fn vmalle1() {
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match () {
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#[cfg(target_arch = "aarch64")]
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() => unsafe { core::arch::asm!("TLBI VMALLE1", options(nostack)) },
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#[cfg(not(target_arch = "aarch64"))]
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() => unimplemented!(),
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}
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}
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/// Invalidate all EL1&0 regime TLB entries in the current VMID
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/// on all PEs in the same Inner Shareable domain.
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///
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/// Executes `TLBI VMALLE1IS`.
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#[inline(always)]
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pub fn vmalle1is() {
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match () {
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#[cfg(target_arch = "aarch64")]
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() => unsafe { core::arch::asm!("TLBI VMALLE1IS", options(nostack)) },
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#[cfg(not(target_arch = "aarch64"))]
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() => unimplemented!(),
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}
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}
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/// Invalidate TLB entries by VA, EL1&0, current VMID.
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///
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/// Executes `TLBI VAE1, <Xt>`.
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///
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/// # Operand Encoding
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///
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/// - Bits \[55:48\]: ASID
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/// - Bits \[43:0\]: VA\[55:12\]
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#[inline(always)]
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pub fn vae1(val: u64) {
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match () {
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#[cfg(target_arch = "aarch64")]
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() => unsafe { core::arch::asm!("TLBI VAE1, {v}", v = in(reg) val, options(nostack)) },
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#[cfg(not(target_arch = "aarch64"))]
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() => {
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let _ = val;
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unimplemented!()
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}
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}
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}
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/// Invalidate TLB entries by VA, EL1&0, current VMID,
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/// Inner Shareable.
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///
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/// Executes `TLBI VAE1IS, <Xt>`.
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///
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/// # Operand Encoding
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///
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/// - Bits \[55:48\]: ASID
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/// - Bits \[43:0\]: VA\[55:12\]
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#[inline(always)]
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pub fn vae1is(val: u64) {
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match () {
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#[cfg(target_arch = "aarch64")]
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() => unsafe { core::arch::asm!("TLBI VAE1IS, {v}", v = in(reg) val, options(nostack)) },
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#[cfg(not(target_arch = "aarch64"))]
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() => {
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let _ = val;
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unimplemented!()
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}
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}
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}
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/// Invalidate TLB entries by VA, last level, EL1&0, current VMID.
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///
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/// Executes `TLBI VALE1, <Xt>`.
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///
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/// Only invalidates entries from the last level of the translation
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/// table walk (leaf entries), which can be more efficient than `vae1`
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/// when intermediate entries are known to be unaffected.
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///
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/// # Operand Encoding
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///
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/// - Bits \[55:48\]: ASID
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/// - Bits \[43:0\]: VA\[55:12\]
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#[inline(always)]
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pub fn vale1(val: u64) {
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match () {
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#[cfg(target_arch = "aarch64")]
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() => unsafe { core::arch::asm!("TLBI VALE1, {v}", v = in(reg) val, options(nostack)) },
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#[cfg(not(target_arch = "aarch64"))]
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() => {
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let _ = val;
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unimplemented!()
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}
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}
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}
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/// Invalidate TLB entries by VA, last level, EL1&0, current VMID,
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/// Inner Shareable.
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///
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/// Executes `TLBI VALE1IS, <Xt>`.
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///
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/// # Operand Encoding
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///
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/// - Bits \[55:48\]: ASID
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/// - Bits \[43:0\]: VA\[55:12\]
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#[inline(always)]
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pub fn vale1is(val: u64) {
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match () {
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#[cfg(target_arch = "aarch64")]
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() => unsafe { core::arch::asm!("TLBI VALE1IS, {v}", v = in(reg) val, options(nostack)) },
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#[cfg(not(target_arch = "aarch64"))]
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() => {
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let _ = val;
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unimplemented!()
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}
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}
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}
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/// Invalidate TLB entries by VA, all ASIDs, EL1&0, current VMID.
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///
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/// Executes `TLBI VAAE1, <Xt>`.
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///
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/// Invalidates entries matching the VA regardless of ASID.
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///
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/// # Operand Encoding
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///
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/// - Bits \[43:0\]: VA\[55:12\]
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#[inline(always)]
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pub fn vaae1(val: u64) {
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match () {
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#[cfg(target_arch = "aarch64")]
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() => unsafe { core::arch::asm!("TLBI VAAE1, {v}", v = in(reg) val, options(nostack)) },
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#[cfg(not(target_arch = "aarch64"))]
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() => {
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let _ = val;
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unimplemented!()
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}
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}
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}
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/// Invalidate TLB entries by VA, all ASIDs, EL1&0, current VMID,
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/// Inner Shareable.
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///
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/// Executes `TLBI VAAE1IS, <Xt>`.
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///
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/// # Operand Encoding
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///
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/// - Bits \[43:0\]: VA\[55:12\]
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#[inline(always)]
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pub fn vaae1is(val: u64) {
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match () {
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#[cfg(target_arch = "aarch64")]
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() => unsafe { core::arch::asm!("TLBI VAAE1IS, {v}", v = in(reg) val, options(nostack)) },
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#[cfg(not(target_arch = "aarch64"))]
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() => {
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let _ = val;
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unimplemented!()
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}
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}
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}
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/// Invalidate TLB entries by VA, all ASIDs, last level, EL1&0,
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/// current VMID.
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///
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/// Executes `TLBI VAALE1, <Xt>`.
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///
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/// # Operand Encoding
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///
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/// - Bits \[43:0\]: VA\[55:12\]
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#[inline(always)]
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pub fn vaale1(val: u64) {
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match () {
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#[cfg(target_arch = "aarch64")]
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() => unsafe { core::arch::asm!("TLBI VAALE1, {v}", v = in(reg) val, options(nostack)) },
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#[cfg(not(target_arch = "aarch64"))]
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() => {
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let _ = val;
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unimplemented!()
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}
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}
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}
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/// Invalidate TLB entries by VA, all ASIDs, last level, EL1&0,
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/// current VMID, Inner Shareable.
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///
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/// Executes `TLBI VAALE1IS, <Xt>`.
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///
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/// # Operand Encoding
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///
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/// - Bits \[43:0\]: VA\[55:12\]
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#[inline(always)]
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pub fn vaale1is(val: u64) {
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match () {
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#[cfg(target_arch = "aarch64")]
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() => unsafe { core::arch::asm!("TLBI VAALE1IS, {v}", v = in(reg) val, options(nostack)) },
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#[cfg(not(target_arch = "aarch64"))]
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() => {
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let _ = val;
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unimplemented!()
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}
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}
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}
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/// Invalidate TLB entries by ASID, EL1&0, current VMID.
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///
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/// Executes `TLBI ASIDE1, <Xt>`.
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///
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/// # Operand Encoding
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///
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/// - Bits \[55:48\]: ASID
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#[inline(always)]
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pub fn aside1(val: u64) {
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match () {
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#[cfg(target_arch = "aarch64")]
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() => unsafe { core::arch::asm!("TLBI ASIDE1, {v}", v = in(reg) val, options(nostack)) },
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#[cfg(not(target_arch = "aarch64"))]
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() => {
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let _ = val;
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unimplemented!()
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}
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}
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}
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/// Invalidate TLB entries by ASID, EL1&0, current VMID,
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/// Inner Shareable.
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///
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/// Executes `TLBI ASIDE1IS, <Xt>`.
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///
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/// # Operand Encoding
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///
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/// - Bits \[55:48\]: ASID
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#[inline(always)]
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pub fn aside1is(val: u64) {
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match () {
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#[cfg(target_arch = "aarch64")]
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() => unsafe { core::arch::asm!("TLBI ASIDE1IS, {v}", v = in(reg) val, options(nostack)) },
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#[cfg(not(target_arch = "aarch64"))]
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() => {
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let _ = val;
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unimplemented!()
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}
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}
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}

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