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Add ID_AA64MMFR3_EL1
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src/registers.rs

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@@ -105,6 +105,7 @@ mod id_aa64isar1_el1;
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mod id_aa64mmfr0_el1;
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mod id_aa64mmfr1_el1;
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mod id_aa64mmfr2_el1;
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mod id_aa64mmfr3_el1;
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mod id_aa64mmfr4_el1;
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mod id_aa64pfr0_el1;
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mod id_aa64pfr1_el1;
@@ -258,6 +259,7 @@ pub use id_aa64isar1_el1::ID_AA64ISAR1_EL1;
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pub use id_aa64mmfr0_el1::ID_AA64MMFR0_EL1;
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pub use id_aa64mmfr1_el1::ID_AA64MMFR1_EL1;
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pub use id_aa64mmfr2_el1::ID_AA64MMFR2_EL1;
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pub use id_aa64mmfr3_el1::ID_AA64MMFR3_EL1;
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pub use id_aa64mmfr4_el1::ID_AA64MMFR4_EL1;
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pub use id_aa64pfr0_el1::ID_AA64PFR0_EL1;
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pub use id_aa64pfr1_el1::ID_AA64PFR1_EL1;

src/registers/id_aa64mmfr3_el1.rs

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// SPDX-License-Identifier: Apache-2.0 OR MIT
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//
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// Copyright (c) 2018-2026 by the author(s)
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//
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// Author(s):
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// - Callum Thomson <callumthom11@gmail.com>
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//! AArch64 Memory Meodel Feature Register 3 - EL1
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use tock_registers::interfaces::Readable;
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use tock_registers::register_bitfields;
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pub struct Reg;
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register_bitfields! {u64,
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pub ID_AA64MMFR3_EL1 [
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/// Speculative behaviour in a PAC authentication failure
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Spec_FPACC OFFSET(60) NUMBITS(4) [
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Undisclosed = 0b0000,
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NoDifference = 0b0001,
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],
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/// Asynchronous Device error exceptions
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ADERR OFFSET(56) NUMBITS(4) [
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DependsOnRASv2 = 0b0000,
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AllExternal = 0b0001,
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DependsOnANERRDependant = 0b0010,
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DependsOnANERRIndependant = 0b0011,
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],
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/// Synchronous Device error exceptions
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SDERR OFFSET(52) NUMBITS(4) [
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DependsOnRASv2 = 0b0000,
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AllExternal = 0b0001,
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DependsOnANERRDependant = 0b0010,
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DependsOnANERRIndependant = 0b0011,
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],
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/// Asynchronous Normal error exceptions
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ANERR OFFSET(44) NUMBITS(4) [
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DependsOnRASv2 = 0b0000,
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AllExternal = 0b0001,
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DependsOnANERRDependant = 0b0010,
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DependsOnANERRIndependant = 0b0011,
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],
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/// Synchronous Normal error exceptions
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SNERR OFFSET(40) NUMBITS(4) [
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DependsOnRASv2 = 0b0000,
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AllExternal = 0b0001,
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DependsOnANERRDependant = 0b0010,
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DependsOnANERRIndependant = 0b0011,
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],
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/// 126-bit translation table descriptor support at stage 2
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D128_2 OFFSET(36) NUMBITS(4) [
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NotSupported = 0b0000,
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Supported = 0b0001,
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],
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/// 126-bit translation table descriptor support
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D128 OFFSET(32) NUMBITS(4) [
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NotSupported = 0b0000,
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Supported = 0b0001,
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],
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/// Support for Memory Encryption Contexts
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MEC OFFSET(28) NUMBITS(4) [
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R_0 = 0b0000,
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R_1 = 0b0001,
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],
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/// Attribute Indexing
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AIE OFFSET(24) NUMBITS(4) [
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NotSupported = 0b0000,
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Supported = 0b0001,
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],
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/// Stage 2 Permission Overlay
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S2POE OFFSET(20) NUMBITS(4) [
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NotSupported = 0b0000,
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Supported = 0b0001,
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],
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/// Stage 1 Permission Overlay
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S1POE OFFSET(16) NUMBITS(4) [
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NotSupported = 0b0000,
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Supported = 0b0001,
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R_2 = 0b0010,
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],
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/// Stage 2 Permission Indirection
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S2PIE OFFSET(12) NUMBITS(4) [
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NotSupported = 0b0000,
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Supported = 0b0001,
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],
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/// Stage 1 Permission Indirection
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S1PIE OFFSET(8) NUMBITS(4) [
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NotSupported = 0b0000,
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Supported = 0b0001,
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],
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/// SCTLR Extension
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SCTLRX OFFSET(4) NUMBITS(4) [
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NotImplemented = 0b0000,
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Implemented = 0b0001,
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],
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/// TCR Extension
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TCRX OFFSET(0) NUMBITS(4) [
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NotImplemented = 0b0000,
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Implemented = 0b0001,
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],
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]
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}
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impl Readable for Reg {
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type T = u64;
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type R = ();
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sys_coproc_read_raw!(u64, "ID_AA64MMFR3_EL1", "x");
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}
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pub const ID_AA64MMFR3_EL1: Reg = Reg;

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