1+ // SPDX-License-Identifier: Apache-2.0 OR MIT
2+ //
3+ // Copyright (c) 2018-2026 by the author(s)
4+ //
5+ // Author(s):
6+ // - Callum Thomson <callumthom11@gmail.com>
7+
8+ //! AArch64 Memory Meodel Feature Register 3 - EL1
9+
10+ use tock_registers:: interfaces:: Readable ;
11+ use tock_registers:: register_bitfields;
12+
13+ pub struct Reg ;
14+
15+ register_bitfields ! { u64 ,
16+ pub ID_AA64MMFR3_EL1 [
17+ /// Speculative behaviour in a PAC authentication failure
18+ Spec_FPACC OFFSET ( 60 ) NUMBITS ( 4 ) [
19+ Undisclosed = 0b0000 ,
20+ NoDifference = 0b0001 ,
21+ ] ,
22+
23+ /// Asynchronous Device error exceptions
24+ ADERR OFFSET ( 56 ) NUMBITS ( 4 ) [
25+ DependsOnRASv2 = 0b0000 ,
26+ AllExternal = 0b0001 ,
27+ DependsOnANERRDependant = 0b0010 ,
28+ DependsOnANERRIndependant = 0b0011 ,
29+ ] ,
30+
31+ /// Synchronous Device error exceptions
32+ SDERR OFFSET ( 52 ) NUMBITS ( 4 ) [
33+ DependsOnRASv2 = 0b0000 ,
34+ AllExternal = 0b0001 ,
35+ DependsOnANERRDependant = 0b0010 ,
36+ DependsOnANERRIndependant = 0b0011 ,
37+ ] ,
38+
39+ /// Asynchronous Normal error exceptions
40+ ANERR OFFSET ( 44 ) NUMBITS ( 4 ) [
41+ DependsOnRASv2 = 0b0000 ,
42+ AllExternal = 0b0001 ,
43+ DependsOnANERRDependant = 0b0010 ,
44+ DependsOnANERRIndependant = 0b0011 ,
45+ ] ,
46+
47+ /// Synchronous Normal error exceptions
48+ SNERR OFFSET ( 40 ) NUMBITS ( 4 ) [
49+ DependsOnRASv2 = 0b0000 ,
50+ AllExternal = 0b0001 ,
51+ DependsOnANERRDependant = 0b0010 ,
52+ DependsOnANERRIndependant = 0b0011 ,
53+ ] ,
54+
55+ /// 126-bit translation table descriptor support at stage 2
56+ D128_2 OFFSET ( 36 ) NUMBITS ( 4 ) [
57+ NotSupported = 0b0000 ,
58+ Supported = 0b0001 ,
59+ ] ,
60+
61+ /// 126-bit translation table descriptor support
62+ D128 OFFSET ( 32 ) NUMBITS ( 4 ) [
63+ NotSupported = 0b0000 ,
64+ Supported = 0b0001 ,
65+ ] ,
66+
67+ /// Support for Memory Encryption Contexts
68+ MEC OFFSET ( 28 ) NUMBITS ( 4 ) [
69+ R_0 = 0b0000 ,
70+ R_1 = 0b0001 ,
71+ ] ,
72+
73+ /// Attribute Indexing
74+ AIE OFFSET ( 24 ) NUMBITS ( 4 ) [
75+ NotSupported = 0b0000 ,
76+ Supported = 0b0001 ,
77+ ] ,
78+
79+ /// Stage 2 Permission Overlay
80+ S2POE OFFSET ( 20 ) NUMBITS ( 4 ) [
81+ NotSupported = 0b0000 ,
82+ Supported = 0b0001 ,
83+ ] ,
84+
85+ /// Stage 1 Permission Overlay
86+ S1POE OFFSET ( 16 ) NUMBITS ( 4 ) [
87+ NotSupported = 0b0000 ,
88+ Supported = 0b0001 ,
89+ R_2 = 0b0010 ,
90+ ] ,
91+
92+ /// Stage 2 Permission Indirection
93+ S2PIE OFFSET ( 12 ) NUMBITS ( 4 ) [
94+ NotSupported = 0b0000 ,
95+ Supported = 0b0001 ,
96+ ] ,
97+
98+ /// Stage 1 Permission Indirection
99+ S1PIE OFFSET ( 8 ) NUMBITS ( 4 ) [
100+ NotSupported = 0b0000 ,
101+ Supported = 0b0001 ,
102+ ] ,
103+
104+ /// SCTLR Extension
105+ SCTLRX OFFSET ( 4 ) NUMBITS ( 4 ) [
106+ NotImplemented = 0b0000 ,
107+ Implemented = 0b0001 ,
108+ ] ,
109+
110+ /// TCR Extension
111+ TCRX OFFSET ( 0 ) NUMBITS ( 4 ) [
112+ NotImplemented = 0b0000 ,
113+ Implemented = 0b0001 ,
114+ ] ,
115+ ]
116+ }
117+
118+ impl Readable for Reg {
119+ type T = u64 ;
120+ type R = ( ) ;
121+
122+ sys_coproc_read_raw ! ( u64 , "ID_AA64MMFR3_EL1" , "x" ) ;
123+ }
124+
125+ pub const ID_AA64MMFR3_EL1 : Reg = Reg ;
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