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Add ID_AA64SMFR0_EL1
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‎src/registers.rs‎

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@@ -109,6 +109,7 @@ mod id_aa64mmfr4_el1;
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mod id_aa64pfr0_el1;
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mod id_aa64pfr1_el1;
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mod id_aa64pfr2_el1;
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mod id_aa64smfr0_el1;
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mod lr;
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mod mair_el1;
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mod mair_el2;
@@ -261,6 +262,7 @@ pub use id_aa64mmfr4_el1::ID_AA64MMFR4_EL1;
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pub use id_aa64pfr0_el1::ID_AA64PFR0_EL1;
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pub use id_aa64pfr1_el1::ID_AA64PFR1_EL1;
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pub use id_aa64pfr2_el1::ID_AA64PFR2_EL1;
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pub use id_aa64smfr0_el1::ID_AA64SMFR0_EL1;
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pub use lr::LR;
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pub use mair_el1::MAIR_EL1;
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pub use mair_el2::MAIR_EL2;

‎src/registers/id_aa64smfr0_el1.rs‎

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// SPDX-License-Identifier: Apache-2.0 OR MIT
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//
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// Copyright (c) 2018-2026 by the author(s)
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//
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// Author(s):
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// - Callum Thomson <callumthom11@gmail.com>
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//! SME Feature ID Register 0 - EL1
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use tock_registers::interfaces::Readable;
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use tock_registers::register_bitfields;
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pub struct Reg;
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register_bitfields! {u64,
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pub ID_AA64SMFR0_EL1 [
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/// Support for Advanced SIMD and SVE instructions in Streaming SVE
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FA64 OFFSET(63) NUMBITS(1) [
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OnlyDefinedLegal = 0b0,
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AllLegal = 0b1,
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],
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/// Support for additional SME2 lookup table instructions
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LUTv2 OFFSET(60) NUMBITS(1) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for SME instructions
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SMEver OFFSET(56) NUMBITS(4) [
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MandatorySME = 0b0000,
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UpToSME2 = 0b0001,
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UpToSME21 = 0b0010,
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UpToSME22 = 0b0011,
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],
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/// Support for SME instructions that accumulate into 64-bit integer elements in the ZA array
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I16I64 OFFSET(52) NUMBITS(4) [
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NotImplemented = 0b0000,
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Implemented = 0b1111,
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],
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/// Support for SME instructions that accumulate into double-precision floating-point elements in the ZA array
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F64F64 OFFSET(48) NUMBITS(1) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for SME2 `SMOPA`, `SMOPS`, `UMOPA` and `UMOPS`
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I16I32 OFFSET(44) NUMBITS(4) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for SME `BFADD`, `BFMLA`, `BFMLS`, `BFMOPA`, `BFMOPS` and `BFSUB`
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B16B16 OFFSET(43) NUMBITS(1) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for SME2 `FMOPA`, `FMOPS`, `FADD`, `FMLA`, `FMLS`, `FSUB`, `FCVT` and `FCVTL`
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F16F16 OFFSET(42) NUMBITS(1) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for the following SME2 instructions:
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/// ZA-targeting FP8 Instructions that accumulate into half-precision floating-point elements
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/// ZA-targeting non-widening half-precision `FADD` and `FSUB`
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F8F16 OFFSET(41) NUMBITS(1) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for SME instructions that accumulate into single-precision floating-point elements
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F8F32 OFFSET(40) NUMBITS(1) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for SME instructions that accumulate 8-bit outer products into 32-bit tiles
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I8I32 OFFSET(36) NUMBITS(4) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for SME `FMOPA` and `FMOPS`
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F16F32 OFFSET(35) NUMBITS(1) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for SME `BFMOPA` and `BFMOPS
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B16F32 OFFSET(34) NUMBITS(1) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for SME `BMOPA` and `BMOPS`
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BI32I32 OFFSET(33) NUMBITS(1) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for SME `FMOPA` and `FMOPS`
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F32F32 OFFSET(32) NUMBITS(1) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for the SVE2 FP8 to single-precision and half-precision multiply-accumulate instructions in Streaming SVE mode
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SF8FMA OFFSET(30) NUMBITS(1) [
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NoEffect = 0b0,
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Implemented = 0b1,
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],
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/// Support for the SVE2 FP8 to single-precision 4-way dot product instruction in Streaming SVE mode
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SF8DP4 OFFSET(29) NUMBITS(1) [
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NoEffect = 0b0,
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Implemented = 0b1,
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],
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/// Support for the SV2 FP8 to half-precision 2-way dot product instructions in Streaming SVE mode
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SF8DP2 OFFSET(28) NUMBITS(1) [
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NoEffect = 0b0,
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Implemented = 0b1,
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],
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/// Support for SVE bit permute instructions in Streaming SVE mode
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SBitPerm OFFSET(25) NUMBITS(1) [
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NoEffect = 0b0,
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Implemented = 0b1,
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],
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/// Support for SVE AES and 128-bit polynomial multiply long instructions in Streaming SVE mode
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AES OFFSET(24) NUMBITS(1) [
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NoEffect = 0b0,
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Supported = 0b1,
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],
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/// Support for FEXPA in Streaming SVE mode
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SFEXPA OFFSET(23) NUMBITS(1) [
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NoEffect = 0b0,
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Supported = 0b1,
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],
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/// Support for some SME Structured sparsity outer product instructions
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STMOP OFFSET(16) NUMBITS(1) [
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NotImplemented = 0b0,
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Implemented = 0b1,
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],
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/// Support for some SME Quarter-time outer product instructions
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SMOP4 OFFSET(0) NUMBITS(1) [
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NotImplmented = 0b0,
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Implemented = 0b1,
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],
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]
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}
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impl Readable for Reg {
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type T = u64;
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type R = ();
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sys_coproc_read_raw!(u64, "ID_AA64SMFR0_EL1", "x");
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}
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pub const ID_AA64SMFR0_EL1: Reg = Reg;

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