Optimize config item test a bit.

wt · wt · commit 1bff304ef029 · 2026-03-25T00:09:44.000-07:00
I used `any(armv6m, armv7m, ...)` in many places where I could have said
`cortex_m` instead for the cfg macro calls. Let's change that.
diff --git a/cortex-m/src/interrupt.rs b/cortex-m/src/interrupt.rs
@@ -1,6 +1,8 @@
 //! Interrupts
 
+#[cfg(cortex_m)]
 use core::arch::asm;
+#[cfg(cortex_m)]
 use core::sync::atomic::{Ordering, compiler_fence};
 
 pub use bare_metal::{CriticalSection, Mutex, Nr};
@@ -37,6 +39,7 @@ unsafe impl<T: Nr + Copy> InterruptNumber for T {
 
 /// Disables all interrupts
 #[inline]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub fn disable() {
     unsafe { asm!("cpsid i", options(nomem, nostack, preserves_flags)) };
 
@@ -50,7 +53,7 @@ pub fn disable() {
 ///
 /// - Do not call this function inside an `interrupt::free` critical section
 #[inline]
-#[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub unsafe fn enable() {
     // Ensure no preceeding memory accesses are reordered to after interrupts are enabled.
     compiler_fence(Ordering::SeqCst);
diff --git a/cortex-m/src/peripheral/scb.rs b/cortex-m/src/peripheral/scb.rs
@@ -308,7 +308,7 @@ impl SCB {
     ///
     /// This operation first invalidates the entire I-cache.
     #[inline]
-    #[cortex_m_macros::asm_cfg(any(armv7m, armv7em, armv8m))]
+    #[cortex_m_macros::asm_cfg(cortex_m)]
     pub fn enable_icache(&mut self) {
         // Don't do anything if I-cache is already enabled
         if Self::icache_enabled() {
@@ -380,7 +380,6 @@ impl SCB {
 
     /// Invalidates the entire I-cache.
     #[inline]
-    #[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
     pub fn invalidate_icache(&mut self) {
         // NOTE(unsafe): No races as all CBP registers are write-only and stateless
         let mut cbp = unsafe { CBP::new() };
@@ -397,7 +396,7 @@ impl SCB {
     /// This operation first invalidates the entire D-cache, ensuring it does
     /// not contain stale values before being enabled.
     #[inline]
-    #[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+    #[cortex_m_macros::asm_cfg(cortex_m)]
     pub fn enable_dcache(&mut self, cpuid: &mut CPUID) {
         // Don't do anything if D-cache is already enabled
         if Self::dcache_enabled() {
diff --git a/cortex-m/src/register/apsr.rs b/cortex-m/src/register/apsr.rs
@@ -1,6 +1,6 @@
 //! Application Program Status Register
 
-#[cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cfg(cortex_m)]
 use core::arch::asm;
 
 /// Application Program Status Register
@@ -51,7 +51,7 @@ impl Apsr {
 ///
 /// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
 #[inline]
-#[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub fn read() -> Apsr {
     let bits;
     unsafe { asm!("mrs {}, APSR", out(reg) bits, options(nomem, nostack, preserves_flags)) };
diff --git a/cortex-m/src/register/control.rs b/cortex-m/src/register/control.rs
@@ -1,8 +1,8 @@
 //! Control register
 
-#[cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cfg(cortex_m)]
 use core::arch::asm;
-#[cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cfg(cortex_m)]
 use core::sync::atomic::{Ordering, compiler_fence};
 
 /// Control register
@@ -178,7 +178,7 @@ impl Fpca {
 
 /// Reads the CPU register
 #[inline]
-#[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub fn read() -> Control {
     let bits;
     unsafe { asm!("mrs {}, CONTROL", out(reg) bits, options(nomem, nostack, preserves_flags)) };
@@ -187,7 +187,7 @@ pub fn read() -> Control {
 
 /// Writes to the CPU register.
 #[inline]
-#[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub unsafe fn write(control: Control) {
     let control = control.bits();
 
diff --git a/cortex-m/src/register/faultmask.rs b/cortex-m/src/register/faultmask.rs
@@ -1,6 +1,6 @@
 //! Fault Mask Register
 
-#[cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cfg(cortex_m)]
 use core::arch::asm;
 
 /// All exceptions are ...
diff --git a/cortex-m/src/register/lr.rs b/cortex-m/src/register/lr.rs
@@ -1,13 +1,13 @@
 //! Link register
 
-#[cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cfg(cortex_m)]
 use core::arch::asm;
 
 /// Reads the CPU register
 ///
 /// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
 #[inline]
-#[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub fn read() -> u32 {
     let r;
     unsafe { asm!("mov {}, lr", out(reg) r, options(nomem, nostack, preserves_flags)) };
@@ -22,7 +22,7 @@ pub fn read() -> u32 {
 /// This function can't be used soundly.
 #[inline]
 #[deprecated = "This function can't be used soundly."]
-#[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub unsafe fn write(bits: u32) {
     unsafe { asm!("mov lr, {}", in(reg) bits, options(nomem, nostack, preserves_flags)) };
 }
diff --git a/cortex-m/src/register/msp.rs b/cortex-m/src/register/msp.rs
@@ -1,11 +1,11 @@
 //! Main Stack Pointer
 
-#[cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cfg(cortex_m)]
 use core::arch::asm;
 
 /// Reads the CPU register
 #[inline]
-#[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub fn read() -> u32 {
     let r;
     unsafe { asm!("mrs {}, MSP", out(reg) r, options(nomem, nostack, preserves_flags)) };
@@ -15,7 +15,7 @@ pub fn read() -> u32 {
 /// Writes `bits` to the CPU register
 #[inline]
 #[deprecated = "calling this function invokes Undefined Behavior, consider asm::bootstrap as an alternative"]
-#[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub unsafe fn write(bits: u32) {
     // Technically is writing to the stack pointer "not pushing any data to the stack"?
     // In any event, if we don't set `nostack` here, this method is useless as the new
diff --git a/cortex-m/src/register/pc.rs b/cortex-m/src/register/pc.rs
@@ -1,13 +1,13 @@
 //! Program counter
 
-#[cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cfg(cortex_m)]
 use core::arch::asm;
 
 /// Reads the CPU register
 ///
 /// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
 #[inline]
-#[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub fn read() -> u32 {
     let r;
     unsafe { asm!("mov {}, pc", out(reg) r, options(nomem, nostack, preserves_flags)) };
@@ -18,7 +18,7 @@ pub fn read() -> u32 {
 ///
 /// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
 #[inline]
-#[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub unsafe fn write(bits: u32) {
     unsafe { asm!("mov pc, {}", in(reg) bits, options(nomem, nostack, preserves_flags)) };
 }
diff --git a/cortex-m/src/register/psp.rs b/cortex-m/src/register/psp.rs
@@ -1,11 +1,11 @@
 //! Process Stack Pointer
 
-#[cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cfg(cortex_m)]
 use core::arch::asm;
 
 /// Reads the CPU register
 #[inline]
-#[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub fn read() -> u32 {
     let r;
     unsafe { asm!("mrs {}, PSP", out(reg) r, options(nomem, nostack, preserves_flags)) };
@@ -14,7 +14,7 @@ pub fn read() -> u32 {
 
 /// Writes `bits` to the CPU register
 #[inline]
-#[cortex_m_macros::asm_cfg(any(armv6m, armv7m, armv7em, armv8m))]
+#[cortex_m_macros::asm_cfg(cortex_m)]
 pub unsafe fn write(bits: u32) {
     // See comment on __msp_w. Unlike MSP, there are legitimate use-cases for modifying PSP
     // if MSP is currently being used as the stack pointer.
