some fixes

Author: robamu

cortex-m/src/peripheral/nvic.rs

@@ -171,11 +171,10 @@ impl NVIC {
         {
             // note(unsafe) atomic read with no side effects
             let nvic = unsafe { Self::steal() };
-            let ipr_index = Self::ipr_index();
-            let iprn_n = nvic
-                .read_ipr(Self::ipr_index(interrupt))
+            let ipr_n = nvic
+                .read_ipr(Self::ipr_index())
                 .expect("unexpected interrupt number");
-            let prio = ((ipr_n >> Self::ipr_shift(interrupt)) & 0x0000_00ff) as u8;
+            ((ipr_n >> Self::ipr_shift(interrupt)) & 0x0000_00ff) as u8
         }
     }
 
@@ -280,7 +279,7 @@ impl NVIC {
         {
             // NOTE(unsafe) atomic stateless write; IPR doesn't store any state
             let nvic = unsafe { Self::steal() };
-            nvic.modify_ipr(Self::ipr_index(interrupt), |mut val| {
+            nvic.modify_ipr(Self::ipr_index(interrupt), |mut value| {
                 let mask = 0x0000_00ff << Self::ipr_shift(interrupt);
                 let prio = u32::from(prio) << Self::ipr_shift(interrupt);