docs improvement

Author: robamu

cortex-m/src/peripheral/nvic.rs

@@ -49,9 +49,7 @@ pub struct RegisterBlock {
     ///
     /// On ARMv7-M, 124 word-sized registers are available. Each of those
     /// contains of 4 interrupt priorities of 8 byte each.The architecture
-    /// specifically allows accessing those along byte boundaries, so they are
-    /// represented as 496 byte-sized registers, for convenience, and to allow
-    /// atomic priority updates.
+    /// specifically allows accessing those along byte boundaries.
     ///
     /// On ARMv6-M, the registers must only be accessed along word boundaries,
     /// so convenient byte-sized representation wouldn't work on that
@@ -63,9 +61,7 @@ pub struct RegisterBlock {
     ///
     /// On ARMv7-M, 124 word-sized registers are available. Each of those
     /// contains of 4 interrupt priorities of 8 byte each.The architecture
-    /// specifically allows accessing those along byte boundaries, so they are
-    /// represented as 496 byte-sized registers, for convenience, and to allow
-    /// atomic priority updates.
+    /// specifically allows accessing those along byte boundaries.
     ///
     /// On ARMv6-M, the registers must only be accessed along word boundaries,
     /// so convenient byte-sized representation wouldn't work on that