fix: Add asm_cfg to all coprocessor instructions

Author: spcan

cortex-m/src/coprocessor.rs

@@ -1,5 +1,7 @@
 //! Coprocessor access assembly instructions.
 
+use cortex_m_macros::asm_cfg;
+
 /// This instruction moves one Register to a Coprocessor Register.
 /// This function generates inline assembly and needs the instruction configuration
 /// during compilation time (i.e. as `const`).
@@ -10,6 +12,7 @@
 ///  - CRN: Coprocessor register N.
 ///  - CRM: Coprocessor register M.
 ///  - OP2: Second optional operation for the coprocessor.
+#[asm_cfg(any(armv7m, armv8m))]
 #[inline(always)]
 pub unsafe fn mcr<const CP: u32, const OP1: u32, const CRN: u32, const CRM: u32, const OP2: u32>(
     value: u32,
@@ -38,6 +41,7 @@ pub unsafe fn mcr<const CP: u32, const OP1: u32, const CRN: u32, const CRM: u32,
 ///  - CRN: Coprocessor register N.
 ///  - CRM: Coprocessor register M.
 ///  - OP2: Second optional operation for the coprocessor.
+#[asm_cfg(any(armv7m, armv8m))]
 #[inline(always)]
 pub unsafe fn mrc<const CP: u32, const OP1: u32, const CRN: u32, const CRM: u32, const OP2: u32>()
 -> u32 {
@@ -67,6 +71,7 @@ pub unsafe fn mrc<const CP: u32, const OP1: u32, const CRN: u32, const CRM: u32,
 ///  - CP: The coprocessor's index.
 ///  - OP1: First optional operation for the coprocessor.
 ///  - CRM: Coprocessor register M.
+#[asm_cfg(any(armv7m, armv8m))]
 #[inline(always)]
 pub unsafe fn mcrr<const CP: u32, const OP1: u32, const CRM: u32>(a: u32, b: u32) {
     unsafe {
@@ -90,6 +95,7 @@ pub unsafe fn mcrr<const CP: u32, const OP1: u32, const CRM: u32>(a: u32, b: u32
 ///  - CP: The coprocessor's index.
 ///  - OP1: First optional operation for the coprocessor.
 ///  - CRM: Coprocessor register M.
+#[asm_cfg(any(armv7m, armv8m))]
 #[inline(always)]
 pub unsafe fn mrrc<const CP: u32, const OPC: u32, const CRM: u32>() -> (u32, u32) {
     // Preallocate the values.