more test fixes, really needs a justfile..

Author: robamu

cortex-m/src/peripheral/nvic.rs

@@ -172,7 +172,7 @@ impl NVIC {
             // note(unsafe) atomic read with no side effects
             let nvic = unsafe { Self::steal() };
             let ipr_n = nvic
-                .read_ipr(Self::ipr_index())
+                .read_ipr(Self::ipr_index(interrupt))
                 .expect("unexpected interrupt number");
             ((ipr_n >> Self::ipr_shift(interrupt)) & 0x0000_00ff) as u8
         }
@@ -278,7 +278,7 @@ impl NVIC {
         #[cfg(armv6m)]
         {
             // NOTE(unsafe) atomic stateless write; IPR doesn't store any state
-            let nvic = unsafe { Self::steal() };
+            let mut nvic = unsafe { Self::steal() };
             nvic.modify_ipr(Self::ipr_index(interrupt), |mut value| {
                 let mask = 0x0000_00ff << Self::ipr_shift(interrupt);
                 let prio = u32::from(prio) << Self::ipr_shift(interrupt);