Move asm code into normal code.

Inline asm has been supported in stable rust for some time, so I removed
the separate asm build infra and added that code to the normal crate code.

Author: wt

cortex-m/asm/inline.rs

@@ -9,127 +9,6 @@
 use core::arch::asm;
 use core::sync::atomic::{Ordering, compiler_fence};
 
-#[inline(always)]
-pub unsafe fn __bkpt() {
-    unsafe { asm!("bkpt", options(nomem, nostack, preserves_flags)) };
-}
-
-#[inline(always)]
-pub unsafe fn __control_r() -> u32 {
-    let r;
-    unsafe { asm!("mrs {}, CONTROL", out(reg) r, options(nomem, nostack, preserves_flags)) };
-    r
-}
-
-#[inline(always)]
-pub unsafe fn __control_w(w: u32) {
-    // ISB is required after writing to CONTROL,
-    // per ARM architectural requirements (see Application Note 321).
-    unsafe {
-        asm!(
-            "msr CONTROL, {}",
-            "isb",
-            in(reg) w,
-            options(nomem, nostack, preserves_flags),
-        )
-    };
-
-    // Ensure memory accesses are not reordered around the CONTROL update.
-    compiler_fence(Ordering::SeqCst);
-}
-
-#[inline(always)]
-pub unsafe fn __cpsid() {
-    unsafe { asm!("cpsid i", options(nomem, nostack, preserves_flags)) };
-
-    // Ensure no subsequent memory accesses are reordered to before interrupts are disabled.
-    compiler_fence(Ordering::SeqCst);
-}
-
-#[inline(always)]
-pub unsafe fn __cpsie() {
-    // Ensure no preceeding memory accesses are reordered to after interrupts are enabled.
-    compiler_fence(Ordering::SeqCst);
-
-    unsafe { asm!("cpsie i", options(nomem, nostack, preserves_flags)) };
-}
-
-#[inline(always)]
-pub unsafe fn __delay(cyc: u32) {
-    // The loop will normally take 3 to 4 CPU cycles per iteration, but superscalar cores
-    // (eg. Cortex-M7) can potentially do it in 2, so we use that as the lower bound, since delaying
-    // for more cycles is okay.
-    // Add 1 to prevent an integer underflow which would cause a long freeze
-    let real_cyc = 1 + cyc / 2;
-    unsafe {
-        asm!(
-            // The `bne` on some cores (eg Cortex-M4) will take a different number of instructions
-            // depending on the alignment of the branch target.  Set the alignment of the top of the
-            // loop to prevent surprising timing changes when the alignment of the delay() changes.
-            ".p2align 3",
-            // Use local labels to avoid R_ARM_THM_JUMP8 relocations which fail on thumbv6m.
-            "1:",
-            "subs {}, #1",
-            "bne 1b",
-            inout(reg) real_cyc => _,
-            options(nomem, nostack),
-        )
-    };
-}
-
-#[inline(always)]
-pub unsafe fn __dmb() {
-    compiler_fence(Ordering::SeqCst);
-    unsafe { asm!("dmb", options(nostack, preserves_flags)) };
-    compiler_fence(Ordering::SeqCst);
-}
-
-#[inline(always)]
-pub unsafe fn __dsb() {
-    compiler_fence(Ordering::SeqCst);
-    unsafe { asm!("dsb", options(nostack, preserves_flags)) };
-    compiler_fence(Ordering::SeqCst);
-}
-
-#[inline(always)]
-pub unsafe fn __isb() {
-    compiler_fence(Ordering::SeqCst);
-    unsafe { asm!("isb", options(nostack, preserves_flags)) };
-    compiler_fence(Ordering::SeqCst);
-}
-
-#[inline(always)]
-pub unsafe fn __msp_r() -> u32 {
-    let r;
-    unsafe { asm!("mrs {}, MSP", out(reg) r, options(nomem, nostack, preserves_flags)) };
-    r
-}
-
-#[inline(always)]
-pub unsafe fn __msp_w(val: u32) {
-    // Technically is writing to the stack pointer "not pushing any data to the stack"?
-    // In any event, if we don't set `nostack` here, this method is useless as the new
-    // stack value is immediately mutated by returning. Really this is just not a good
-    // method and its higher-level use is marked as deprecated in cortex-m.
-    unsafe { asm!("msr MSP, {}", in(reg) val, options(nomem, nostack, preserves_flags)) };
-}
-
-// NOTE: No FFI shim, this requires inline asm.
-#[inline(always)]
-pub unsafe fn __apsr_r() -> u32 {
-    let r;
-    unsafe { asm!("mrs {}, APSR", out(reg) r, options(nomem, nostack, preserves_flags)) };
-    r
-}
-
-#[inline(always)]
-pub unsafe fn __nop() {
-    // NOTE: This is a `pure` asm block, but applying that option allows the compiler to eliminate
-    // the nop entirely (or to collapse multiple subsequent ones). Since the user probably wants N
-    // nops when they call `nop` N times, let's not add that option.
-    unsafe { asm!("nop", options(nomem, nostack, preserves_flags)) };
-}
-
 // NOTE: No FFI shim, this requires inline asm.
 #[inline(always)]
 pub unsafe fn __pc_r() -> u32 {

cortex-m/asm/lib.rs

@@ -52,18 +52,6 @@ macro_rules! shims {
 }
 
 shims! {
-    fn __bkpt();
-    fn __control_r() -> u32;
-    fn __control_w(w: u32);
-    fn __cpsid();
-    fn __cpsie();
-    fn __delay(cyc: u32);
-    fn __dmb();
-    fn __dsb();
-    fn __isb();
-    fn __msp_r() -> u32;
-    fn __msp_w(val: u32);
-    fn __nop();
     fn __primask_r() -> u32;
     fn __psp_r() -> u32;
     fn __psp_w(val: u32);

cortex-m/src/asm.rs

@@ -6,13 +6,15 @@
 #[path = "../asm/inline.rs"]
 pub(crate) mod inline;
 
+pub(crate) mod inner;
+
 /// Puts the processor in Debug state. Debuggers can pick this up as a "breakpoint".
 ///
 /// **NOTE** calling `bkpt` when the processor is not connected to a debugger will cause an
 /// exception.
 #[inline(always)]
 pub fn bkpt() {
-    call_asm!(__bkpt());
+    unsafe { inner::__bkpt() };
 }
 
 /// Blocks the program for *at least* `cycles` CPU cycles.
@@ -31,7 +33,7 @@ pub fn bkpt() {
 /// please use a more accurate method to produce a delay.
 #[inline]
 pub fn delay(cycles: u32) {
-    call_asm!(__delay(cycles: u32));
+    unsafe { inner::__delay(cycles) };
 }
 
 /// A no-operation. Useful to prevent delay loops from being optimized away.
@@ -72,7 +74,7 @@ pub fn sev() {
 /// from cache or memory, after the instruction has been completed.
 #[inline]
 pub fn isb() {
-    call_asm!(__isb())
+    unsafe { self::inner::__isb() }
 }
 
 /// Data Synchronization Barrier
@@ -84,7 +86,7 @@ pub fn isb() {
 ///  * all cache and branch predictor maintenance operations before this instruction complete
 #[inline]
 pub fn dsb() {
-    call_asm!(__dsb())
+    unsafe { self::inner::__dsb() }
 }
 
 /// Data Memory Barrier
@@ -94,7 +96,7 @@ pub fn dsb() {
 /// after the `DMB` instruction.
 #[inline]
 pub fn dmb() {
-    call_asm!(__dmb())
+    unsafe { self::inner::__dmb() }
 }
 
 /// Test Target

cortex-m/src/asm/inner.rs

@@ -0,0 +1,123 @@
+use core::arch::asm;
+use core::sync::atomic::{Ordering, compiler_fence};
+
+#[inline(always)]
+pub unsafe fn __bkpt() {
+    unsafe { asm!("bkpt", options(nomem, nostack, preserves_flags)) };
+}
+
+#[inline(always)]
+pub unsafe fn __control_r() -> u32 {
+    let r;
+    unsafe { asm!("mrs {}, CONTROL", out(reg) r, options(nomem, nostack, preserves_flags)) };
+    r
+}
+
+#[inline(always)]
+pub unsafe fn __control_w(w: u32) {
+    // ISB is required after writing to CONTROL,
+    // per ARM architectural requirements (see Application Note 321).
+    unsafe {
+        asm!(
+            "msr CONTROL, {}",
+            "isb",
+            in(reg) w,
+            options(nomem, nostack, preserves_flags),
+        )
+    };
+
+    // Ensure memory accesses are not reordered around the CONTROL update.
+    compiler_fence(Ordering::SeqCst);
+}
+
+#[inline(always)]
+pub unsafe fn __cpsid() {
+    unsafe { asm!("cpsid i", options(nomem, nostack, preserves_flags)) };
+
+    // Ensure no subsequent memory accesses are reordered to before interrupts are disabled.
+    compiler_fence(Ordering::SeqCst);
+}
+
+#[inline(always)]
+pub unsafe fn __cpsie() {
+    // Ensure no preceeding memory accesses are reordered to after interrupts are enabled.
+    compiler_fence(Ordering::SeqCst);
+
+    unsafe { asm!("cpsie i", options(nomem, nostack, preserves_flags)) };
+}
+
+#[inline(always)]
+pub unsafe fn __delay(cyc: u32) {
+    // The loop will normally take 3 to 4 CPU cycles per iteration, but superscalar cores
+    // (eg. Cortex-M7) can potentially do it in 2, so we use that as the lower bound, since delaying
+    // for more cycles is okay.
+    // Add 1 to prevent an integer underflow which would cause a long freeze
+    let real_cyc = 1 + cyc / 2;
+    unsafe {
+        asm!(
+            // The `bne` on some cores (eg Cortex-M4) will take a different number of instructions
+            // depending on the alignment of the branch target.  Set the alignment of the top of the
+            // loop to prevent surprising timing changes when the alignment of the delay() changes.
+            ".p2align 3",
+            // Use local labels to avoid R_ARM_THM_JUMP8 relocations which fail on thumbv6m.
+            "2:", // not 1 or 0 because of https://bugs.llvm.org/show_bug.cgi?id=36144
+            "subs {}, #1",
+            "bne 1b",
+            inout(reg) real_cyc => _,
+            options(nomem, nostack),
+        )
+    };
+}
+
+#[inline(always)]
+pub unsafe fn __dmb() {
+    compiler_fence(Ordering::SeqCst);
+    unsafe { asm!("dmb", options(nostack, preserves_flags)) };
+    compiler_fence(Ordering::SeqCst);
+}
+
+#[inline(always)]
+pub unsafe fn __dsb() {
+    compiler_fence(Ordering::SeqCst);
+    unsafe { asm!("dsb", options(nostack, preserves_flags)) };
+    compiler_fence(Ordering::SeqCst);
+}
+
+#[inline(always)]
+pub unsafe fn __isb() {
+    compiler_fence(Ordering::SeqCst);
+    unsafe { asm!("isb", options(nostack, preserves_flags)) };
+    compiler_fence(Ordering::SeqCst);
+}
+
+#[inline(always)]
+pub unsafe fn __msp_r() -> u32 {
+    let r;
+    unsafe { asm!("mrs {}, MSP", out(reg) r, options(nomem, nostack, preserves_flags)) };
+    r
+}
+
+#[inline(always)]
+pub unsafe fn __msp_w(val: u32) {
+    // Technically is writing to the stack pointer "not pushing any data to the stack"?
+    // In any event, if we don't set `nostack` here, this method is useless as the new
+    // stack value is immediately mutated by returning. Really this is just not a good
+    // method and its higher-level use is marked as deprecated in cortex-m.
+    unsafe { asm!("msr MSP, {}", in(reg) val, options(nomem, nostack, preserves_flags)) };
+}
+
+// NOTE: No FFI shim, this requires inline asm.
+#[inline(always)]
+pub unsafe fn __apsr_r() -> u32 {
+    let r;
+    unsafe { asm!("mrs {}, APSR", out(reg) r, options(nomem, nostack, preserves_flags)) };
+    r
+}
+
+#[inline(always)]
+pub unsafe fn __nop() {
+    // NOTE: This is a `pure` asm block, but applying that option allows the compiler to eliminate
+    // the nop entirely (or to collapse multiple subsequent ones). Since the user probably wants N
+    // nops when they call `nop` N times, let's not add that option.
+    unsafe { asm!("nop", options(nomem, nostack, preserves_flags)) };
+}

cortex-m/src/interrupt.rs

@@ -35,7 +35,7 @@ unsafe impl<T: Nr + Copy> InterruptNumber for T {
 /// Disables all interrupts
 #[inline]
 pub fn disable() {
-    call_asm!(__cpsid());
+    unsafe { crate::asm::inner::__cpsid() };
 }
 
 /// Enables all the interrupts
@@ -45,7 +45,7 @@ pub fn disable() {
 /// - Do not call this function inside an `interrupt::free` critical section
 #[inline]
 pub unsafe fn enable() {
-    call_asm!(__cpsie());
+    unsafe { crate::asm::inner::__cpsie() };
 }
 
 /// Execute closure `f` in an interrupt-free context.

cortex-m/src/register/apsr.rs

@@ -49,6 +49,6 @@ impl Apsr {
 /// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
 #[inline]
 pub fn read() -> Apsr {
-    let bits: u32 = call_asm!(__apsr_r() -> u32);
+    let bits = unsafe { crate::asm::inner::__apsr_r() };
     Apsr { bits }
 }

cortex-m/src/register/control.rs

@@ -174,13 +174,13 @@ impl Fpca {
 /// Reads the CPU register
 #[inline]
 pub fn read() -> Control {
-    let bits: u32 = call_asm!(__control_r() -> u32);
+    let bits = unsafe { crate::asm::inner::__control_r() };
     Control { bits }
 }
 
 /// Writes to the CPU register.
 #[inline]
 pub unsafe fn write(control: Control) {
     let control = control.bits();
-    call_asm!(__control_w(control: u32));
+    unsafe { crate::asm::inner::__control_w(control) };
 }

cortex-m/src/register/msp.rs

@@ -3,14 +3,14 @@
 /// Reads the CPU register
 #[inline]
 pub fn read() -> u32 {
-    call_asm!(__msp_r() -> u32)
+    unsafe { crate::asm::inner::__msp_r() }
 }
 
 /// Writes `bits` to the CPU register
 #[inline]
 #[deprecated = "calling this function invokes Undefined Behavior, consider asm::bootstrap as an alternative"]
 pub unsafe fn write(bits: u32) {
-    call_asm!(__msp_w(bits: u32));
+    unsafe { crate::asm::inner::__msp_w(bits) }
 }
 
 /// Reads the Non-Secure CPU register from Secure state.