We should think about how a I3C Trait may be implemented. This may be done like the CAN Trait in an extra crate allowing breakage and only when it really stabilized to be merged into the core hal.
Currently there aren't a lot of IC's using the protocol, but it seems to get adoption. Major Suppliers have started incorporating it into their new designs, including NXP, STM, Renesas, Nordic Semi, Espressif, Texas Instruments, Bosch and Microchip. See here for a list.
This is supposed to be a place where we can discuss how this might be implemented. The specification can be found here. However it can only be accessed by providing an E-Mail Adresse and then only the public version instead of the member version.
The protocol itself is combining the advantages of I2C and SPI. It is downwards compatibel to I2C and starts adressing like it, however when it is clear that only the an I3C device is adressed it switches to a push pull architecture to enable higher transfer speeds like SPI. There is also an option to send an interupt over the Bus for Devices, which should probably be represented in the API. It does however only support 7 Bit Adressing for the I2C compatibility mode.
We should think about how a I3C Trait may be implemented. This may be done like the CAN Trait in an extra crate allowing breakage and only when it really stabilized to be merged into the core hal.
Currently there aren't a lot of IC's using the protocol, but it seems to get adoption. Major Suppliers have started incorporating it into their new designs, including NXP, STM, Renesas, Nordic Semi, Espressif, Texas Instruments, Bosch and Microchip. See here for a list.
This is supposed to be a place where we can discuss how this might be implemented. The specification can be found here. However it can only be accessed by providing an E-Mail Adresse and then only the public version instead of the member version.
The protocol itself is combining the advantages of I2C and SPI. It is downwards compatibel to I2C and starts adressing like it, however when it is clear that only the an I3C device is adressed it switches to a push pull architecture to enable higher transfer speeds like SPI. There is also an option to send an interupt over the Bus for Devices, which should probably be represented in the API. It does however only support 7 Bit Adressing for the I2C compatibility mode.