Add f16 vector support (#513)

folkertdev · calebzulawski · web-flow · commit 0557e3478104 · 2026-04-11T11:13:30.000-04:00
* Add `f16` vector support * run `cargo update` * disable `f16` tests on wasm32 with simd128 llvm hangs in that case, see llvm/llvm-project#189251 * Add reference to LLVM issue causing f16 wasm ICE --------- Co-authored-by: Caleb Zulawski <caleb.zulawski@gmail.com>
diff --git a/Cargo.lock b/Cargo.lock
diff --git a/Cargo.toml b/Cargo.toml
@@ -11,3 +11,8 @@ opt-level = 2
 
 [profile.test.package.test_helpers]
 opt-level = 2
+
+[workspace.dependencies.proptest]
+version = "1.11"
+default-features = false
+features = ["alloc", "f16"]
diff --git a/crates/core_simd/Cargo.toml b/crates/core_simd/Cargo.toml
@@ -18,9 +18,7 @@ wasm-bindgen = "0.2"
 wasm-bindgen-test = "0.3"
 
 [dev-dependencies.proptest]
-version = "1.0"
-default-features = false
-features = ["alloc"]
+workspace = true
 
 # Enable the `wasm_js` feature so that getrandom works on wasm32-unknown-unknown.
 [dev-dependencies.getrandom]
diff --git a/crates/core_simd/src/alias.rs b/crates/core_simd/src/alias.rs
@@ -153,6 +153,16 @@ alias! {
         usizex64 64
     }
 
+    f16 = {
+        f16x1 1
+        f16x2 2
+        f16x4 4
+        f16x8 8
+        f16x16 16
+        f16x32 32
+        f16x64 64
+    }
+
     f32 = {
         f32x1 1
         f32x2 2
diff --git a/crates/core_simd/src/cast.rs b/crates/core_simd/src/cast.rs
@@ -44,6 +44,9 @@ impl SimdCast for u64 {}
 unsafe impl Sealed for usize {}
 impl SimdCast for usize {}
 // Safety: primitive number types can be cast to other primitive number types
+unsafe impl Sealed for f16 {}
+impl SimdCast for f16 {}
+// Safety: primitive number types can be cast to other primitive number types
 unsafe impl Sealed for f32 {}
 impl SimdCast for f32 {}
 // Safety: primitive number types can be cast to other primitive number types
diff --git a/crates/core_simd/src/lib.rs b/crates/core_simd/src/lib.rs
@@ -1,6 +1,7 @@
 #![no_std]
 #![feature(
     convert_float_to_int,
+    f16,
     core_intrinsics,
     decl_macro,
     repr_simd,
diff --git a/crates/core_simd/src/ops.rs b/crates/core_simd/src/ops.rs
@@ -245,7 +245,7 @@ for_base_ops! {
 // We don't need any special precautions here:
 // Floats always accept arithmetic ops, but may become NaN.
 for_base_ops! {
-    T = (f32, f64);
+    T = (f16, f32, f64);
     type Lhs = Simd<T, N>;
     type Rhs = Simd<T, N>;
     type Output = Self;
diff --git a/crates/core_simd/src/ops/unary.rs b/crates/core_simd/src/ops/unary.rs
@@ -19,6 +19,8 @@ macro_rules! neg {
 }
 
 neg! {
+    impl<const N: usize> Neg for Simd<f16, N>
+
     impl<const N: usize> Neg for Simd<f32, N>
 
     impl<const N: usize> Neg for Simd<f64, N>
diff --git a/crates/core_simd/src/simd/cmp/eq.rs b/crates/core_simd/src/simd/cmp/eq.rs
@@ -42,7 +42,7 @@ macro_rules! impl_number {
     }
 }
 
-impl_number! { f32, f64, u8, u16, u32, u64, usize, i8, i16, i32, i64, isize }
+impl_number! { f16, f32, f64, u8, u16, u32, u64, usize, i8, i16, i32, i64, isize }
 
 macro_rules! impl_mask {
     { $($integer:ty),* } => {
diff --git a/crates/core_simd/src/simd/cmp/ord.rs b/crates/core_simd/src/simd/cmp/ord.rs
@@ -144,7 +144,7 @@ macro_rules! impl_float {
     }
 }
 
-impl_float! { f32, f64 }
+impl_float! { f16, f32, f64 }
 
 macro_rules! impl_mask {
     { $($integer:ty),* } => {
diff --git a/crates/core_simd/src/simd/num/float.rs b/crates/core_simd/src/simd/num/float.rs
@@ -444,4 +444,4 @@ macro_rules! impl_trait {
     }
 }
 
-impl_trait! { f32 { bits: u32, mask: i32 }, f64 { bits: u64, mask: i64 } }
+impl_trait! { f16 { bits: u16, mask: i16 }, f32 { bits: u32, mask: i32 }, f64 { bits: u64, mask: i64 } }
diff --git a/crates/core_simd/src/vector.rs b/crates/core_simd/src/vector.rs
@@ -1146,6 +1146,13 @@ unsafe impl SimdElement for isize {
     type Mask = isize;
 }
 
+impl Sealed for f16 {}
+
+// Safety: f16 is a valid SIMD element type, and is supported by this API
+unsafe impl SimdElement for f16 {
+    type Mask = i16;
+}
+
 impl Sealed for f32 {}
 
 // Safety: f32 is a valid SIMD element type, and is supported by this API
diff --git a/crates/core_simd/tests/f16_ops.rs b/crates/core_simd/tests/f16_ops.rs
@@ -0,0 +1,10 @@
+#![feature(portable_simd)]
+#![feature(f16)]
+
+#[macro_use]
+mod ops_macros;
+
+// FIXME: some f16 operations cause rustc to hang on wasm simd
+// https://github.com/llvm/llvm-project/issues/189251
+#[cfg(not(all(target_arch = "wasm32", target_feature = "simd128")))]
+impl_float_tests! { f16, i16 }
diff --git a/crates/std_float/src/lib.rs b/crates/std_float/src/lib.rs
@@ -2,6 +2,7 @@
     feature = "as_crate",
     feature(core_intrinsics),
     feature(portable_simd),
+    feature(f16),
     allow(internal_features)
 )]
 #[cfg(not(feature = "as_crate"))]
@@ -169,9 +170,17 @@ pub trait StdFloat: Sealed + Sized {
     fn fract(self) -> Self;
 }
 
+impl<const N: usize> Sealed for Simd<f16, N> {}
 impl<const N: usize> Sealed for Simd<f32, N> {}
 impl<const N: usize> Sealed for Simd<f64, N> {}
 
+impl<const N: usize> StdFloat for Simd<f16, N> {
+    #[inline]
+    fn fract(self) -> Self {
+        self - self.trunc()
+    }
+}
+
 impl<const N: usize> StdFloat for Simd<f32, N> {
     #[inline]
     fn fract(self) -> Self {
diff --git a/crates/test_helpers/Cargo.toml b/crates/test_helpers/Cargo.toml
@@ -5,5 +5,5 @@ edition = "2021"
 publish = false
 
 [dependencies]
-proptest = { version = "1.0", default-features = false, features = ["alloc", "std"] }
+proptest = { workspace = true, features = ["alloc", "std"] }
 float-cmp = "0.10"
diff --git a/crates/test_helpers/src/biteq.rs b/crates/test_helpers/src/biteq.rs
@@ -53,7 +53,7 @@ macro_rules! impl_float_biteq {
     };
 }
 
-impl_float_biteq! { f32, f64 }
+impl_float_biteq! { f16, f32, f64 }
 
 impl<T> BitEq for *const T {
     fn biteq(&self, other: &Self) -> bool {
diff --git a/crates/test_helpers/src/lib.rs b/crates/test_helpers/src/lib.rs
@@ -1,3 +1,4 @@
+#![feature(f16)]
 #![cfg_attr(
     any(target_arch = "powerpc", target_arch = "powerpc64"),
     feature(powerpc_target_feature, stdarch_powerpc)
@@ -46,6 +47,7 @@ impl_num! { u16 }
 impl_num! { u32 }
 impl_num! { u64 }
 impl_num! { usize }
+impl_num! { f16 }
 impl_num! { f32 }
 impl_num! { f64 }
 
diff --git a/crates/test_helpers/src/subnormals.rs b/crates/test_helpers/src/subnormals.rs
@@ -39,7 +39,7 @@ macro_rules! impl_else {
     }
 }
 
-impl_float! { f32, f64 }
+impl_float! { f16, f32, f64 }
 impl_else! { i8, i16, i32, i64, isize, u8, u16, u32, u64, usize }
 
 /// AltiVec should flush subnormal inputs to zero, but QEMU seems to only flush outputs.

Original file line number	Diff line number	Diff line change
`@@ -19,6 +19,8 @@ macro_rules! neg {`
`19`	`19`	`}`
`20`	`20`
`21`	`21`	`neg! {`
	`22`	`+ impl<const N: usize> Neg for Simd<f16, N>`
	`23`	`+`
`22`	`24`	`impl<const N: usize> Neg for Simd<f32, N>`
`23`	`25`
`24`	`26`	`impl<const N: usize> Neg for Simd<f64, N>`
Original file line number	Diff line number	Diff line change
`@@ -42,7 +42,7 @@ macro_rules! impl_number {`
`42`	`42`	`}`
`43`	`43`	`}`
`44`	`44`
`45`		`-impl_number! { f32, f64, u8, u16, u32, u64, usize, i8, i16, i32, i64, isize }`
	`45`	`+impl_number! { f16, f32, f64, u8, u16, u32, u64, usize, i8, i16, i32, i64, isize }`
`46`	`46`
`47`	`47`	`macro_rules! impl_mask {`
`48`	`48`	`{ $($integer:ty),* } => {`
Original file line number	Diff line number	Diff line change
`@@ -144,7 +144,7 @@ macro_rules! impl_float {`
`144`	`144`	`}`
`145`	`145`	`}`
`146`	`146`
`147`		`-impl_float! { f32, f64 }`
	`147`	`+impl_float! { f16, f32, f64 }`
`148`	`148`
`149`	`149`	`macro_rules! impl_mask {`
`150`	`150`	`{ $($integer:ty),* } => {`