Rollup merge of #157137 - taiki-e:powerpcspe, r=RalfJung

rustc_target: Use +spe for powerpcspe targets

LLVM does not infer this from the target name and `abi: "spe"` is just for cfg.  To actually generate the correct instructions for these targets (without `-C target-cpu`), we need to pass `+spe` to LLVM.

Fixes #138960
See also #157085
Related #137860

cc @RalfJung
cc @BKPepe ([powerpc-unknown-linux-muslspe target maintainer](https://doc.rust-lang.org/nightly/rustc/platform-support/powerpc-unknown-linux-muslspe.html#target-maintainers))
cc @glaubitz (who added powerpc-unknown-linux-gnuspe in #48484)
cc @biabbas @hax0kartik ([*-wrs-vxworks target maintainers](https://doc.rust-lang.org/nightly/rustc/platform-support/vxworks.html#target-maintainers))

@rustbot label +O-PowerPC +A-target-feature

Author: JonathanBrouwer

compiler/rustc_target/src/spec/targets/powerpc_unknown_linux_gnuspe.rs

@@ -25,7 +25,7 @@ pub(crate) fn target() -> Target {
         options: TargetOptions {
             cfg_abi: CfgAbi::Spe,
             endian: Endian::Big,
-            features: "+secure-plt,+msync".into(),
+            features: "+secure-plt,+msync,+spe".into(),
             mcount: "_mcount".into(),
             ..base
         },

compiler/rustc_target/src/spec/targets/powerpc_unknown_linux_muslspe.rs

@@ -25,7 +25,7 @@ pub(crate) fn target() -> Target {
         options: TargetOptions {
             cfg_abi: CfgAbi::Spe,
             endian: Endian::Big,
-            features: "+msync".into(),
+            features: "+msync,+spe".into(),
             mcount: "_mcount".into(),
             ..base
         },

compiler/rustc_target/src/spec/targets/powerpc_wrs_vxworks_spe.rs

@@ -26,7 +26,7 @@ pub(crate) fn target() -> Target {
             cfg_abi: CfgAbi::Spe,
             endian: Endian::Big,
             // feature msync would disable instruction 'fsync' which is not supported by fsl_p1p2
-            features: "+secure-plt,+msync".into(),
+            features: "+secure-plt,+msync,+spe".into(),
             ..base
         },
     }