Commit 4472d4c
Submodule llvm-project updated 60 files
- clang/docs/ClangCommandLineReference.rst+1-1
- clang/docs/ReleaseNotes.rst+5-1
- clang/include/clang/Driver/Options.td+1-1
- clang/lib/CodeGen/CGExpr.cpp+12-2
- clang/lib/Driver/ToolChains/Arch/AArch64.cpp+3
- clang/test/CodeGen/fread-inline-builtin-late-redecl.c+26
- compiler-rt/lib/asan/asan_linux.cpp+12-18
- compiler-rt/lib/builtins/clear_cache.c+4-1
- libcxx/include/__support/openbsd/xlocale.h+20
- lld/COFF/DebugTypes.cpp+5-1
- lld/ELF/Writer.cpp+24-17
- lld/test/ELF/emit-relocs-synthetic.s+54
- llvm/include/llvm/CodeGen/FastISel.h+7
- llvm/include/llvm/CodeGen/SelectionDAG.h+13
- llvm/include/llvm/CodeGen/SelectionDAGISel.h+1
- llvm/lib/CodeGen/MachineFunction.cpp-3
- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp+2-2
- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp+3-2
- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h+2-1
- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp+2-1
- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp+2-1
- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp+9-1
- llvm/lib/Target/AArch64/AArch64.td+5
- llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp+34
- llvm/lib/Target/AArch64/AArch64FastISel.cpp+8
- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp+9-1
- llvm/lib/Target/AArch64/AArch64ISelLowering.h+2
- llvm/lib/Target/AArch64/AArch64InstrInfo.td+11
- llvm/lib/Target/AArch64/AArch64Subtarget.h+6
- llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp+10-2
- llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp+24-39
- llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp+2
- llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp+2
- llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h+4
- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp+2-2
- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp+11-2
- llvm/lib/Target/PowerPC/PPCInstrInfo.td+2-2
- llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp+5-3
- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp+28-26
- llvm/lib/Target/RISCV/RISCVISelLowering.cpp+40-31
- llvm/lib/Target/X86/X86ISelLowering.cpp+8-13
- llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp+17
- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp+7-8
- llvm/test/CodeGen/AArch64/setjmp-bti-no-enforcement.ll+51
- llvm/test/CodeGen/AArch64/setjmp-bti-outliner.ll+83
- llvm/test/CodeGen/AArch64/setjmp-bti.ll+55
- llvm/test/CodeGen/RISCV/imm.ll+36
- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll+37
- llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll+34
- llvm/test/DebugInfo/X86/instr-ref-opt-bisect.ll+117
- llvm/test/MC/PowerPC/ppc64-abs-reloc.s+22
- llvm/test/MC/RISCV/align-option-relax.s+8
- llvm/test/MC/RISCV/align.s+8
- llvm/test/Transforms/InstCombine/ashr-lshr.ll+40-40
- llvm/test/Transforms/InstCombine/logical-select.ll+2-2
- llvm/test/Transforms/InstCombine/truncating-saturate.ll+2-2
- llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll+46
- llvm/test/tools/llvm-mt/notify_update.test+16
- llvm/tools/llvm-mt/Opts.td+1-1
- llvm/tools/llvm-mt/llvm-mt.cpp+24-1
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