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Rationalise the Armv7-A, Armv7-R and Armv8-R bare-metal target configs
1 parent a2bc948 commit 52cb2ba

5 files changed

Lines changed: 31 additions & 100 deletions

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‎compiler/rustc_target/src/spec/targets/armv7a_none_eabi.rs‎

Lines changed: 10 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1,39 +1,8 @@
1-
// Generic ARMv7-A target for bare-metal code - floating point disabled
2-
//
3-
// This is basically the `armv7-unknown-linux-gnueabi` target with some changes
4-
// (listed below) to bring it closer to the bare-metal `thumb` & `aarch64`
5-
// targets:
6-
//
7-
// - `TargetOptions.features`: added `+strict-align`. rationale: unaligned
8-
// memory access is disabled on boot on these cores
9-
// - linker changed to LLD. rationale: C is not strictly needed to build
10-
// bare-metal binaries (the `gcc` linker has the advantage that it knows where C
11-
// libraries and crt*.o are but it's not much of an advantage here); LLD is also
12-
// faster
13-
// - `panic_strategy` set to `abort`. rationale: matches `thumb` targets
14-
// - `relocation-model` set to `static`; also no PIE, no relro and no dynamic
15-
// linking. rationale: matches `thumb` targets
1+
// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
162

17-
use crate::spec::{
18-
Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
19-
TargetOptions,
20-
};
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
214

225
pub(crate) fn target() -> Target {
23-
let opts = TargetOptions {
24-
abi: Abi::Eabi,
25-
llvm_floatabi: Some(FloatAbi::Soft),
26-
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
27-
linker: Some("rust-lld".into()),
28-
features: "+v7,+thumb2,+soft-float,-neon,+strict-align".into(),
29-
relocation_model: RelocModel::Static,
30-
disable_redzone: true,
31-
max_atomic_width: Some(64),
32-
panic_strategy: PanicStrategy::Abort,
33-
emit_debug_gdb_scripts: false,
34-
c_enum_min_bits: Some(8),
35-
..Default::default()
36-
};
376
Target {
387
llvm_target: "armv7a-none-eabi".into(),
398
metadata: TargetMetadata {
@@ -45,6 +14,13 @@ pub(crate) fn target() -> Target {
4514
pointer_width: 32,
4615
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
4716
arch: Arch::Arm,
48-
options: opts,
17+
options: TargetOptions {
18+
abi: Abi::Eabi,
19+
llvm_floatabi: Some(FloatAbi::Soft),
20+
features: "+v7,+thumb2,+soft-float,-neon,+strict-align".into(),
21+
max_atomic_width: Some(64),
22+
has_thumb_interworking: true,
23+
..base::arm_none::opts()
24+
},
4925
}
5026
}

‎compiler/rustc_target/src/spec/targets/armv7a_none_eabihf.rs‎

Lines changed: 10 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1,31 +1,8 @@
1-
// Generic ARMv7-A target for bare-metal code - floating point enabled (assumes
2-
// FPU is present and emits FPU instructions)
3-
//
4-
// This is basically the `armv7-unknown-linux-gnueabihf` target with some
5-
// changes (list in `armv7a_none_eabi.rs`) to bring it closer to the bare-metal
6-
// `thumb` & `aarch64` targets.
1+
// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
72

8-
use crate::spec::{
9-
Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
10-
TargetOptions,
11-
};
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
124

135
pub(crate) fn target() -> Target {
14-
let opts = TargetOptions {
15-
abi: Abi::EabiHf,
16-
llvm_floatabi: Some(FloatAbi::Hard),
17-
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
18-
linker: Some("rust-lld".into()),
19-
features: "+v7,+vfp3d16,+thumb2,-neon,+strict-align".into(),
20-
relocation_model: RelocModel::Static,
21-
disable_redzone: true,
22-
max_atomic_width: Some(64),
23-
panic_strategy: PanicStrategy::Abort,
24-
emit_debug_gdb_scripts: false,
25-
// GCC defaults to 8 for arm-none here.
26-
c_enum_min_bits: Some(8),
27-
..Default::default()
28-
};
296
Target {
307
llvm_target: "armv7a-none-eabihf".into(),
318
metadata: TargetMetadata {
@@ -37,6 +14,13 @@ pub(crate) fn target() -> Target {
3714
pointer_width: 32,
3815
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
3916
arch: Arch::Arm,
40-
options: opts,
17+
options: TargetOptions {
18+
abi: Abi::EabiHf,
19+
llvm_floatabi: Some(FloatAbi::Hard),
20+
features: "+v7,+vfp3d16,+thumb2,-neon,+strict-align".into(),
21+
max_atomic_width: Some(64),
22+
has_thumb_interworking: true,
23+
..base::arm_none::opts()
24+
},
4125
}
4226
}

‎compiler/rustc_target/src/spec/targets/armv7r_none_eabi.rs‎

Lines changed: 4 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,35 +1,25 @@
11
// Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R)
22

3-
use crate::spec::{
4-
Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
5-
TargetOptions,
6-
};
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
74

85
pub(crate) fn target() -> Target {
96
Target {
107
llvm_target: "armv7r-none-eabi".into(),
118
metadata: TargetMetadata {
12-
description: Some("Armv7-R".into()),
9+
description: Some("Bare Armv7-R".into()),
1310
tier: Some(2),
1411
host_tools: Some(false),
1512
std: Some(false),
1613
},
1714
pointer_width: 32,
1815
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
1916
arch: Arch::Arm,
20-
2117
options: TargetOptions {
2218
abi: Abi::Eabi,
2319
llvm_floatabi: Some(FloatAbi::Soft),
24-
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
25-
linker: Some("rust-lld".into()),
26-
relocation_model: RelocModel::Static,
27-
panic_strategy: PanicStrategy::Abort,
2820
max_atomic_width: Some(64),
29-
emit_debug_gdb_scripts: false,
30-
// GCC defaults to 8 for arm-none here.
31-
c_enum_min_bits: Some(8),
32-
..Default::default()
21+
has_thumb_interworking: true,
22+
..base::arm_none::opts()
3323
},
3424
}
3525
}

‎compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs‎

Lines changed: 4 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,26 @@
11
// Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R)
22

3-
use crate::spec::{
4-
Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
5-
TargetOptions,
6-
};
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
74

85
pub(crate) fn target() -> Target {
96
Target {
107
llvm_target: "armv7r-none-eabihf".into(),
118
metadata: TargetMetadata {
12-
description: Some("Armv7-R, hardfloat".into()),
9+
description: Some("Bare Armv7-R, hardfloat".into()),
1310
tier: Some(2),
1411
host_tools: Some(false),
1512
std: Some(false),
1613
},
1714
pointer_width: 32,
1815
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
1916
arch: Arch::Arm,
20-
2117
options: TargetOptions {
2218
abi: Abi::EabiHf,
2319
llvm_floatabi: Some(FloatAbi::Hard),
24-
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
25-
linker: Some("rust-lld".into()),
26-
relocation_model: RelocModel::Static,
27-
panic_strategy: PanicStrategy::Abort,
2820
features: "+vfp3d16".into(),
2921
max_atomic_width: Some(64),
30-
emit_debug_gdb_scripts: false,
31-
// GCC defaults to 8 for arm-none here.
32-
c_enum_min_bits: Some(8),
33-
..Default::default()
22+
has_thumb_interworking: true,
23+
..base::arm_none::opts()
3424
},
3525
}
3626
}

‎compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs‎

Lines changed: 3 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,6 @@
11
// Targets the Little-endian Cortex-R52 processor (ARMv8-R)
22

3-
use crate::spec::{
4-
Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
5-
TargetOptions,
6-
};
3+
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
74

85
pub(crate) fn target() -> Target {
96
Target {
@@ -21,10 +18,6 @@ pub(crate) fn target() -> Target {
2118
options: TargetOptions {
2219
abi: Abi::EabiHf,
2320
llvm_floatabi: Some(FloatAbi::Hard),
24-
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
25-
linker: Some("rust-lld".into()),
26-
relocation_model: RelocModel::Static,
27-
panic_strategy: PanicStrategy::Abort,
2821
// Armv8-R requires a minimum set of floating-point features equivalent to:
2922
// fp-armv8, SP-only, with 16 DP (32 SP) registers
3023
// LLVM defines Armv8-R to include these features automatically.
@@ -36,10 +29,8 @@ pub(crate) fn target() -> Target {
3629
// Arm Cortex-R52 Processor Technical Reference Manual
3730
// - Chapter 15 Advanced SIMD and floating-point support
3831
max_atomic_width: Some(64),
39-
emit_debug_gdb_scripts: false,
40-
// GCC defaults to 8 for arm-none here.
41-
c_enum_min_bits: Some(8),
42-
..Default::default()
32+
has_thumb_interworking: true,
33+
..base::arm_none::opts()
4334
},
4435
}
4536
}

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