Auto merge of #150722 - nikic:llvm-22, r=<try>

Update to LLVM 22

Author: rust-bors[bot]

.gitmodules

@@ -24,8 +24,8 @@
 	shallow = true
 [submodule "src/llvm-project"]
 	path = src/llvm-project
-	url = https://github.com/rust-lang/llvm-project.git
-	branch = rustc/21.1-2025-08-01
+	url = https://github.com/nikic/llvm-project.git
+	branch = rust-llvm-22
 	shallow = true
 [submodule "src/doc/embedded-book"]
 	path = src/doc/embedded-book

compiler/rustc_codegen_llvm/src/builder.rs

@@ -1773,6 +1773,9 @@ impl<'a, 'll, 'tcx> Builder<'a, 'll, 'tcx> {
         }
 
         if crate::llvm_util::get_version() >= (22, 0, 0) {
+            // LLVM 22 requires the lifetime intrinsic to act directly on the alloca,
+            // there can't be an addrspacecast in between.
+            let ptr = unsafe { llvm::LLVMRustStripPointerCasts(ptr) };
             self.call_intrinsic(intrinsic, &[self.val_ty(ptr)], &[ptr]);
         } else {
             self.call_intrinsic(intrinsic, &[self.val_ty(ptr)], &[self.cx.const_u64(size), ptr]);

compiler/rustc_codegen_llvm/src/context.rs

@@ -211,6 +211,15 @@ pub(crate) unsafe fn create_module<'ll>(
             // LLVM 22 updated the NVPTX layout to indicate 256-bit vector load/store: https://github.com/llvm/llvm-project/pull/155198
             target_data_layout = target_data_layout.replace("-i256:256", "");
         }
+        if sess.target.arch == Arch::PowerPC64 {
+            // LLVM 22 updated the ABI alignment for double on AIX: https://github.com/llvm/llvm-project/pull/144673
+            target_data_layout = target_data_layout.replace("-f64:32:64", "");
+        }
+        if sess.target.arch == Arch::AmdGpu {
+            // LLVM 22 specified ELF mangling in the amdgpu data layout:
+            // https://github.com/llvm/llvm-project/pull/163011
+            target_data_layout = target_data_layout.replace("-e:m", "");
+        }
     }
 
     // Ensure the data-layout values hardcoded remain the defaults.

compiler/rustc_codegen_llvm/src/llvm/ffi.rs

@@ -1959,6 +1959,7 @@ unsafe extern "C" {
         Metadata: &'a Metadata,
     );
     pub(crate) fn LLVMRustIsNonGVFunctionPointerTy(Val: &Value) -> bool;
+    pub(crate) fn LLVMRustStripPointerCasts<'a>(Val: &'a Value) -> &'a Value;
 
     // Operations on scalar constants
     pub(crate) fn LLVMRustConstIntGetZExtValue(ConstantVal: &ConstantInt, Value: &mut u64) -> bool;

compiler/rustc_llvm/llvm-wrapper/RustWrapper.cpp

@@ -1745,6 +1745,10 @@ extern "C" bool LLVMRustIsNonGVFunctionPointerTy(LLVMValueRef V) {
   return false;
 }
 
+extern "C" LLVMValueRef LLVMRustStripPointerCasts(LLVMValueRef V) {
+  return wrap(unwrap(V)->stripPointerCasts());
+}
+
 extern "C" bool LLVMRustLLVMHasZlibCompression() {
   return llvm::compression::zlib::isAvailable();
 }

compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs

@@ -5,7 +5,7 @@ use crate::spec::{
 pub(crate) fn target() -> Target {
     Target {
         arch: Arch::AmdGpu,
-        data_layout: "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9".into(),
+        data_layout: "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9".into(),
         llvm_target: "amdgcn-amd-amdhsa".into(),
         metadata: TargetMetadata {
             description: Some("AMD GPU".into()),

compiler/rustc_target/src/spec/targets/powerpc64_ibm_aix.rs

@@ -17,7 +17,8 @@ pub(crate) fn target() -> Target {
             std: None, // ?
         },
         pointer_width: 64,
-        data_layout: "E-m:a-Fi64-i64:64-i128:128-n32:64-S128-v256:256:256-v512:512:512".into(),
+        data_layout: "E-m:a-Fi64-i64:64-i128:128-n32:64-f64:32:64-S128-v256:256:256-v512:512:512"
+            .into(),
         arch: Arch::PowerPC64,
         options: base,
     }

src/llvm-project

@@ -3,14 +3,23 @@
 //@ compile-flags: --crate-type=rlib --target=amdgcn-amd-amdhsa -Ctarget-cpu=gfx900
 //@ needs-llvm-components: amdgpu
 //@ add-minicore
+//@ revisions: LLVM21 LLVM22
+//@ [LLVM21] max-llvm-major-version: 21
+//@ [LLVM22] min-llvm-version: 22
 #![feature(no_core)]
 #![no_core]
 
 extern crate minicore;
 
+// Make sure that on LLVM 22, the alloca is passed directly to the lifetime intrinsics,
+// not the addrspacecast.
+
 // CHECK-LABEL: @ref_of_local
 // CHECK: [[alloca:%[0-9]]] = alloca
 // CHECK: %i = addrspacecast ptr addrspace(5) [[alloca]] to ptr
+// LLVM22: call void @llvm.lifetime.start.p5(ptr addrspace(5) [[alloca]])
+// CHECK: call void %f(ptr{{.*}}%i)
+// LLVM22: call void @llvm.lifetime.end.p5(ptr addrspace(5) [[alloca]])
 #[no_mangle]
 pub fn ref_of_local(f: fn(&i32)) {
     let i = 0;