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Auto merge of #157759 - JonathanBrouwer:rollup-Pz5ncKJ, r=<try>
Rollup of 13 pull requests try-job: dist-various-1 try-job: test-various try-job: x86_64-gnu-aux try-job: x86_64-gnu-llvm-21-3 try-job: x86_64-msvc-1 try-job: aarch64-apple try-job: x86_64-mingw-1 try-job: i686-msvc-2
2 parents 32cfe53 + 0feb094 commit dd3f3f1

181 files changed

Lines changed: 3156 additions & 2265 deletions

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Cargo.lock

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4894,6 +4894,7 @@ version = "0.0.0"
48944894
dependencies = [
48954895
"proc-macro2",
48964896
"quote",
4897+
"rustc_data_structures",
48974898
"syn",
48984899
"synstructure",
48994900
]

compiler/rustc_borrowck/src/lib.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -650,7 +650,7 @@ pub(crate) struct BorrowckInferCtxt<'tcx> {
650650

651651
impl<'tcx> BorrowckInferCtxt<'tcx> {
652652
pub(crate) fn new(tcx: TyCtxt<'tcx>, def_id: LocalDefId, root_def_id: LocalDefId) -> Self {
653-
let typing_mode = if tcx.use_typing_mode_borrowck() {
653+
let typing_mode = if tcx.use_typing_mode_post_typeck_until_borrowck() {
654654
TypingMode::borrowck(tcx, def_id)
655655
} else {
656656
TypingMode::analysis_in_body(tcx, def_id)

compiler/rustc_borrowck/src/region_infer/opaque_types/mod.rs

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -261,8 +261,8 @@ fn collect_defining_uses<'tcx>(
261261
DefiningScopeKind::MirBorrowck,
262262
) {
263263
// A non-defining use. This is a hard error on stable and gets ignored
264-
// with `TypingMode::Borrowck`.
265-
if infcx.tcx.use_typing_mode_borrowck() {
264+
// with `TypingMode::PostTypeckUntilBorrowck`.
265+
if infcx.tcx.use_typing_mode_post_typeck_until_borrowck() {
266266
match err {
267267
NonDefiningUseReason::Tainted(guar) => add_hidden_type(
268268
infcx.tcx,
@@ -327,7 +327,7 @@ fn compute_definition_site_hidden_types_from_defining_uses<'tcx>(
327327
// If we're using the next solver, the unconstrained region may be resolved by a
328328
// fully defining use from another body.
329329
// So we don't generate error eagerly here.
330-
if rcx.infcx.tcx.use_typing_mode_borrowck() {
330+
if rcx.infcx.tcx.use_typing_mode_post_typeck_until_borrowck() {
331331
unconstrained_hidden_type_errors.push(UnexpectedHiddenRegion {
332332
def_id,
333333
hidden_type,
@@ -366,7 +366,7 @@ fn compute_definition_site_hidden_types_from_defining_uses<'tcx>(
366366
// the hidden type becomes the opaque type itself. In this case, this was an opaque
367367
// usage of the opaque type and we can ignore it. This check is mirrored in typeck's
368368
// writeback.
369-
if !rcx.infcx.tcx.use_typing_mode_borrowck() {
369+
if !rcx.infcx.tcx.use_typing_mode_post_typeck_until_borrowck() {
370370
if let &ty::Alias(ty::AliasTy { kind: ty::Opaque { def_id }, args, .. }) =
371371
hidden_type.ty.skip_binder().kind()
372372
&& def_id == opaque_type_key.def_id.to_def_id()
@@ -540,7 +540,7 @@ pub(crate) fn apply_definition_site_hidden_types<'tcx>(
540540
let mut errors = Vec::new();
541541
for &(key, hidden_type) in opaque_types {
542542
let Some(expected) = hidden_types.get(&key.def_id) else {
543-
if !tcx.use_typing_mode_borrowck() {
543+
if !tcx.use_typing_mode_post_typeck_until_borrowck() {
544544
if let &ty::Alias(ty::AliasTy { kind: ty::Opaque { def_id }, args, .. }) =
545545
hidden_type.ty.kind()
546546
&& def_id == key.def_id.to_def_id()

compiler/rustc_codegen_gcc/src/asm.rs

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -677,6 +677,8 @@ fn reg_class_to_gcc(reg_class: InlineAsmRegClass) -> &'static str {
677677
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
678678
unreachable!("clobber-only")
679679
}
680+
InlineAsmRegClass::Amdgpu(AmdgpuInlineAsmRegClass::Sgpr(_)) => "Sg",
681+
InlineAsmRegClass::Amdgpu(AmdgpuInlineAsmRegClass::Vgpr(_)) => "v",
680682
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => "r",
681683
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
682684
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
@@ -785,6 +787,7 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
785787
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
786788
unreachable!("clobber-only")
787789
}
790+
InlineAsmRegClass::Amdgpu(_) => cx.type_i32(),
788791
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => cx.type_i32(),
789792
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
790793
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => cx.type_f32(),
@@ -993,6 +996,7 @@ fn modifier_to_gcc(
993996
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
994997
unreachable!("clobber-only")
995998
}
999+
InlineAsmRegClass::Amdgpu(_) => None,
9961000
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => None,
9971001
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
9981002
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => None,

compiler/rustc_codegen_gcc/src/debuginfo.rs

Lines changed: 12 additions & 139 deletions
Original file line numberDiff line numberDiff line change
@@ -3,13 +3,9 @@ use std::sync::Arc;
33

44
use gccjit::{Function, Location, RValue};
55
use rustc_abi::Size;
6-
use rustc_codegen_ssa::mir::debuginfo::{DebugScope, FunctionDebugContext, VariableKind};
6+
use rustc_codegen_ssa::mir::debuginfo::VariableKind;
77
use rustc_codegen_ssa::traits::{DebugInfoBuilderMethods, DebugInfoCodegenMethods};
8-
use rustc_index::bit_set::DenseBitSet;
9-
use rustc_index::{Idx, IndexVec};
10-
use rustc_middle::mir::{self, Body, SourceScope};
118
use rustc_middle::ty::{ExistentialTraitRef, Instance, Ty};
12-
use rustc_session::config::DebugInfo;
139
use rustc_span::{BytePos, Pos, SourceFile, SourceFileAndLine, Span, Symbol};
1410
use rustc_target::callconv::FnAbi;
1511

@@ -65,115 +61,6 @@ impl<'a, 'gcc, 'tcx> DebugInfoBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
6561
}
6662
}
6763

68-
/// Generate the `debug_context` in an MIR Body.
69-
/// # Source of Origin
70-
/// Copied from `create_scope_map.rs` of rustc_codegen_llvm
71-
fn compute_mir_scopes<'gcc, 'tcx>(
72-
cx: &CodegenCx<'gcc, 'tcx>,
73-
instance: Instance<'tcx>,
74-
mir: &Body<'tcx>,
75-
debug_context: &mut FunctionDebugContext<'tcx, (), Location<'gcc>>,
76-
) {
77-
// Find all scopes with variables defined in them.
78-
let variables = if cx.sess().opts.debuginfo == DebugInfo::Full {
79-
let mut vars = DenseBitSet::new_empty(mir.source_scopes.len());
80-
// FIXME(eddyb) take into account that arguments always have debuginfo,
81-
// irrespective of their name (assuming full debuginfo is enabled).
82-
// NOTE(eddyb) actually, on second thought, those are always in the
83-
// function scope, which always exists.
84-
for var_debug_info in &mir.var_debug_info {
85-
vars.insert(var_debug_info.source_info.scope);
86-
}
87-
Some(vars)
88-
} else {
89-
// Nothing to emit, of course.
90-
None
91-
};
92-
let mut instantiated = DenseBitSet::new_empty(mir.source_scopes.len());
93-
// Instantiate all scopes.
94-
for idx in 0..mir.source_scopes.len() {
95-
let scope = SourceScope::new(idx);
96-
make_mir_scope(cx, instance, mir, &variables, debug_context, &mut instantiated, scope);
97-
}
98-
assert!(instantiated.count() == mir.source_scopes.len());
99-
}
100-
101-
/// Update the `debug_context`, adding new scope to it,
102-
/// if it's not added as is denoted in `instantiated`.
103-
///
104-
/// # Source of Origin
105-
/// Copied from `create_scope_map.rs` of rustc_codegen_llvm
106-
/// FIXME(tempdragon/?): Add Scope Support Here.
107-
fn make_mir_scope<'gcc, 'tcx>(
108-
cx: &CodegenCx<'gcc, 'tcx>,
109-
_instance: Instance<'tcx>,
110-
mir: &Body<'tcx>,
111-
variables: &Option<DenseBitSet<SourceScope>>,
112-
debug_context: &mut FunctionDebugContext<'tcx, (), Location<'gcc>>,
113-
instantiated: &mut DenseBitSet<SourceScope>,
114-
scope: SourceScope,
115-
) {
116-
if instantiated.contains(scope) {
117-
return;
118-
}
119-
120-
let scope_data = &mir.source_scopes[scope];
121-
let parent_scope = if let Some(parent) = scope_data.parent_scope {
122-
make_mir_scope(cx, _instance, mir, variables, debug_context, instantiated, parent);
123-
debug_context.scopes[parent]
124-
} else {
125-
// The root is the function itself.
126-
let file = cx.sess().source_map().lookup_source_file(mir.span.lo());
127-
debug_context.scopes[scope] = DebugScope {
128-
file_start_pos: file.start_pos,
129-
file_end_pos: file.end_position(),
130-
..debug_context.scopes[scope]
131-
};
132-
instantiated.insert(scope);
133-
return;
134-
};
135-
136-
if let Some(ref vars) = *variables
137-
&& !vars.contains(scope)
138-
&& scope_data.inlined.is_none()
139-
{
140-
// Do not create a DIScope if there are no variables defined in this
141-
// MIR `SourceScope`, and it's not `inlined`, to avoid debuginfo bloat.
142-
debug_context.scopes[scope] = parent_scope;
143-
instantiated.insert(scope);
144-
return;
145-
}
146-
147-
let loc = cx.lookup_debug_loc(scope_data.span.lo());
148-
149-
// FIXME(tempdragon): Add the scope related code here if the scope is supported.
150-
let dbg_scope = ();
151-
152-
let inlined_at = scope_data.inlined.map(|(_, callsite_span)| {
153-
// FIXME(eddyb) this doesn't account for the macro-related
154-
// `Span` fixups that `rustc_codegen_ssa::mir::debuginfo` does.
155-
156-
// FIXME(tempdragon): Add scope support and then revert to cg_llvm version of this closure
157-
// NOTE: These variables passed () here.
158-
// Changed to comply to clippy.
159-
160-
/* let callsite_scope = */
161-
parent_scope.adjust_dbg_scope_for_span(cx, callsite_span);
162-
cx.dbg_loc(/* callsite_scope */ (), parent_scope.inlined_at, callsite_span)
163-
});
164-
let p_inlined_at = parent_scope.inlined_at;
165-
// FIXME(tempdragon): dbg_scope: Add support for scope extension here.
166-
inlined_at.or(p_inlined_at);
167-
168-
debug_context.scopes[scope] = DebugScope {
169-
dbg_scope,
170-
inlined_at,
171-
file_start_pos: loc.file.start_pos,
172-
file_end_pos: loc.file.end_position(),
173-
};
174-
instantiated.insert(scope);
175-
}
176-
17764
/// A source code location used to generate debug information.
17865
// FIXME(eddyb) rename this to better indicate it's a duplicate of
17966
// `rustc_span::Loc` rather than `DILocation`, perhaps by making
@@ -228,33 +115,19 @@ impl<'gcc, 'tcx> DebugInfoCodegenMethods<'tcx> for CodegenCx<'gcc, 'tcx> {
228115
// FIXME(antoyo)
229116
}
230117

231-
fn create_function_debug_context(
118+
fn dbg_create_lexical_block(
232119
&self,
233-
instance: Instance<'tcx>,
234-
fn_abi: &FnAbi<'tcx, Ty<'tcx>>,
235-
llfn: Function<'gcc>,
236-
mir: &mir::Body<'tcx>,
237-
) -> Option<FunctionDebugContext<'tcx, Self::DIScope, Self::DILocation>> {
238-
if self.sess().opts.debuginfo == DebugInfo::None {
239-
return None;
240-
}
241-
242-
// Initialize fn debug context (including scopes).
243-
let empty_scope = DebugScope {
244-
dbg_scope: self.dbg_scope_fn(instance, fn_abi, Some(llfn)),
245-
inlined_at: None,
246-
file_start_pos: BytePos(0),
247-
file_end_pos: BytePos(0),
248-
};
249-
let mut fn_debug_context = FunctionDebugContext {
250-
scopes: IndexVec::from_elem(empty_scope, mir.source_scopes.as_slice()),
251-
inlined_function_scopes: Default::default(),
252-
};
253-
254-
// Fill in all the scopes, with the information from the MIR body.
255-
compute_mir_scopes(self, instance, mir, &mut fn_debug_context);
120+
_pos: BytePos,
121+
_parent_scope: Self::DIScope,
122+
) -> Self::DIScope {
123+
}
256124

257-
Some(fn_debug_context)
125+
fn dbg_location_clone_with_discriminator(
126+
&self,
127+
loc: Self::DILocation,
128+
_discriminator: u32,
129+
) -> Option<Self::DILocation> {
130+
Some(loc)
258131
}
259132

260133
fn extend_scope_to_file(

compiler/rustc_codegen_gcc/src/lib.rs

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,6 @@ extern crate rustc_data_structures;
3030
extern crate rustc_errors;
3131
extern crate rustc_fs_util;
3232
extern crate rustc_hir;
33-
extern crate rustc_index;
3433
#[cfg(feature = "master")]
3534
extern crate rustc_interface;
3635
extern crate rustc_log;

compiler/rustc_codegen_llvm/src/asm.rs

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
4343
match *op {
4444
InlineAsmOperandRef::Out { reg, late, place } => {
4545
let is_target_supported = |reg_class: InlineAsmRegClass| {
46-
for &(_, feature) in reg_class.supported_types(asm_arch, true) {
46+
for &(_, feature) in reg_class.supported_types(asm_arch, true).as_ref() {
4747
if let Some(feature) = feature {
4848
if self
4949
.tcx
@@ -229,6 +229,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
229229
InlineAsmArch::AArch64 | InlineAsmArch::Arm64EC | InlineAsmArch::Arm => {
230230
constraints.push("~{cc}".to_string());
231231
}
232+
InlineAsmArch::Amdgpu => {}
232233
InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
233234
constraints.extend_from_slice(&[
234235
"~{dirflag}".to_string(),
@@ -699,6 +700,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
699700
| Arm(ArmInlineAsmRegClass::dreg_low8)
700701
| Arm(ArmInlineAsmRegClass::qreg_low4) => "x",
701702
Arm(ArmInlineAsmRegClass::dreg) | Arm(ArmInlineAsmRegClass::qreg) => "w",
703+
Amdgpu(AmdgpuInlineAsmRegClass::Sgpr(_)) => "s",
704+
Amdgpu(AmdgpuInlineAsmRegClass::Vgpr(_)) => "v",
702705
Hexagon(HexagonInlineAsmRegClass::reg) => "r",
703706
Hexagon(HexagonInlineAsmRegClass::reg_pair) => "r",
704707
Hexagon(HexagonInlineAsmRegClass::preg) => unreachable!("clobber-only"),
@@ -809,6 +812,7 @@ fn modifier_to_llvm(
809812
modifier
810813
}
811814
}
815+
Amdgpu(_) => None,
812816
Hexagon(_) => None,
813817
LoongArch(_) => None,
814818
Mips(_) => None,
@@ -890,6 +894,7 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
890894
Arm(ArmInlineAsmRegClass::qreg)
891895
| Arm(ArmInlineAsmRegClass::qreg_low8)
892896
| Arm(ArmInlineAsmRegClass::qreg_low4) => cx.type_vector(cx.type_i64(), 2),
897+
Amdgpu(_) => cx.type_i32(),
893898
Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
894899
Hexagon(HexagonInlineAsmRegClass::reg_pair) => cx.type_i64(),
895900
Hexagon(HexagonInlineAsmRegClass::preg) => unreachable!("clobber-only"),

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