Skip to content

Commit e025fc9

Browse files
Rollup merge of #151572 - androm3da:bcain/abi_cconv, r=wesleywiser
Fix Hexagon ABI calling convention for small aggregates Small structs (<= 64 bits) were being passed with their fields split into separate arguments instead of being packed into register-sized chunks. This caused ABI mismatches. The fix properly casts small aggregates to consecutive register-sized chunks using Uniform::consecutive(), matching the Hexagon C ABI where small structs are packed into R1:0 register pair. This fixes tests like extern-pass-TwoU16s.rs and extern-pass-TwoU8s.rs.
2 parents cea42a6 + b1925a9 commit e025fc9

1 file changed

Lines changed: 50 additions & 10 deletions

File tree

compiler/rustc_target/src/callconv/hexagon.rs

Lines changed: 50 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,76 @@
1-
use rustc_abi::TyAbiInterface;
1+
use rustc_abi::{HasDataLayout, TyAbiInterface};
22

3-
use crate::callconv::{ArgAbi, FnAbi};
3+
use crate::callconv::{ArgAbi, FnAbi, Reg, Uniform};
44

5-
fn classify_ret<Ty>(ret: &mut ArgAbi<'_, Ty>) {
6-
if ret.layout.is_aggregate() && ret.layout.size.bits() > 64 {
7-
ret.make_indirect();
8-
} else {
5+
fn classify_ret<'a, Ty, C>(_cx: &C, ret: &mut ArgAbi<'a, Ty>)
6+
where
7+
Ty: TyAbiInterface<'a, C> + Copy,
8+
C: HasDataLayout,
9+
{
10+
if !ret.layout.is_sized() {
11+
return;
12+
}
13+
14+
if !ret.layout.is_aggregate() {
915
ret.extend_integer_width_to(32);
16+
return;
17+
}
18+
19+
// Per the Hexagon ABI:
20+
// - Aggregates up to 32 bits are returned in R0
21+
// - Aggregates 33-64 bits are returned in R1:R0
22+
// - Aggregates > 64 bits are returned indirectly via hidden first argument
23+
let size = ret.layout.size;
24+
let bits = size.bits();
25+
if bits <= 32 {
26+
ret.cast_to(Uniform::new(Reg::i32(), size));
27+
} else if bits <= 64 {
28+
ret.cast_to(Uniform::new(Reg::i64(), size));
29+
} else {
30+
ret.make_indirect();
1031
}
1132
}
1233

1334
fn classify_arg<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>)
1435
where
1536
Ty: TyAbiInterface<'a, C> + Copy,
37+
C: HasDataLayout,
1638
{
39+
if !arg.layout.is_sized() {
40+
return;
41+
}
1742
if arg.layout.pass_indirectly_in_non_rustic_abis(cx) {
1843
arg.make_indirect();
1944
return;
2045
}
21-
if arg.layout.is_aggregate() && arg.layout.size.bits() > 64 {
22-
arg.make_indirect();
23-
} else {
46+
47+
if !arg.layout.is_aggregate() {
2448
arg.extend_integer_width_to(32);
49+
return;
50+
}
51+
52+
// Per the Hexagon ABI:
53+
// - Aggregates up to 32 bits are passed in a single register
54+
// - Aggregates 33-64 bits are passed in a register pair
55+
// - Aggregates > 64 bits are passed on the stack
56+
let size = arg.layout.size;
57+
let bits = size.bits();
58+
if bits <= 32 {
59+
arg.cast_to(Uniform::new(Reg::i32(), size));
60+
} else if bits <= 64 {
61+
arg.cast_to(Uniform::new(Reg::i64(), size));
62+
} else {
63+
arg.pass_by_stack_offset(None);
2564
}
2665
}
2766

2867
pub(crate) fn compute_abi_info<'a, Ty, C>(cx: &C, fn_abi: &mut FnAbi<'a, Ty>)
2968
where
3069
Ty: TyAbiInterface<'a, C> + Copy,
70+
C: HasDataLayout,
3171
{
3272
if !fn_abi.ret.is_ignore() {
33-
classify_ret(&mut fn_abi.ret);
73+
classify_ret(cx, &mut fn_abi.ret);
3474
}
3575

3676
for arg in fn_abi.args.iter_mut() {

0 commit comments

Comments
 (0)