From 519a5559ff6fa4b714361f97e48cc0bd2f4cd484 Mon Sep 17 00:00:00 2001
From: Kcang-gna <kcang_gna@163.com>
Date: Sun, 5 Apr 2026 15:36:36 +0800
Subject: [PATCH] add regression test for Redundant memory strores with mut
 parameters in by-value returns

---
 .../riscv-redundant-memory-stores.rs          | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 tests/assembly-llvm/riscv-redundant-memory-stores.rs

diff --git a/tests/assembly-llvm/riscv-redundant-memory-stores.rs b/tests/assembly-llvm/riscv-redundant-memory-stores.rs
new file mode 100644
index 0000000000000..acdb69d33fd1e
--- /dev/null
+++ b/tests/assembly-llvm/riscv-redundant-memory-stores.rs
@@ -0,0 +1,33 @@
+//! Regression test for <https://github.com/rust-lang/rust/issues/149762>:
+
+//@ assembly-output: emit-asm
+//@ compile-flags: -Copt-level=3 --target riscv64gc-unknown-linux-gnu
+//@ needs-llvm-components: riscv
+//@ only-riscv64
+
+pub struct SomeComplexType {
+    a: u64,
+    b: u64,
+    c: u64,
+}
+
+// CHECK-LABEL: with_mut_param
+#[no_mangle]
+pub fn with_mut_param(mut a: SomeComplexType) -> SomeComplexType {
+    // CHECK: ld a2, 0(a1)
+    // CHECK-NEXT: ld a3, 8(a1)
+    // CHECK-NEXT: ld a4, 16(a1)
+    // CHECK-NEXT: addi a2, a2, 10
+    // CHECK-NEXT: addi a3, a3, 2
+    // CHECK-NEXT: sd a2, 0(a1)
+    // CHECK-NEXT: sd a3, 8(a1)
+    // CHECK-NEXT: sd a2, 0(a0)
+    // CHECK-NEXT: sd a3, 8(a0)
+    // CHECK-NEXT: sd a4, 16(a0)
+    // CHECK-NEXT: ret
+    a.a += 10;
+    a.b += 2;
+    a
+}
+
+fn main() {}