Integrate stdarch tests for aarch64

Author: CathalMullan

build_system/prepare.rs

@@ -12,6 +12,7 @@ pub(crate) fn prepare(dirs: &Dirs) {
     crate::tests::RAND_REPO.fetch(dirs);
     crate::tests::REGEX_REPO.fetch(dirs);
     crate::tests::GRAVIOLA_REPO.fetch(dirs);
+    crate::tests::STDARCH_REPO.fetch(dirs);
 }
 
 pub(crate) struct GitRepo {

build_system/stdarch_skip/aarch64_core.txt

@@ -0,0 +1,301 @@
+vaba_s16
+vaba_s32
+vaba_s8
+vaba_u16
+vaba_u32
+vaba_u8
+vabaq_s16
+vabaq_s32
+vabaq_s8
+vabaq_u16
+vabaq_u32
+vabaq_u8
+vhadd_s16
+vhadd_s32
+vhadd_s8
+vhadd_u16
+vhadd_u32
+vhadd_u8
+vhaddq_s16
+vhaddq_s32
+vhaddq_s8
+vhaddq_u16
+vhaddq_u32
+vhaddq_u8
+vhsub_s16
+vhsub_s32
+vhsub_s8
+vhsub_u16
+vhsub_u32
+vhsub_u8
+vhsubq_s16
+vhsubq_s32
+vhsubq_s8
+vhsubq_u16
+vhsubq_u32
+vhsubq_u8
+vld1_f16_x2
+vld1_f16_x3
+vld1_f16_x4
+vld1_f32_x2
+vld1_f32_x3
+vld1_f32_x4
+vld1_f64_x2
+vld1_f64_x3
+vld1_f64_x4
+vld1_p16_x2
+vld1_p16_x3
+vld1_p16_x4
+vld1_p64_x2
+vld1_p64_x3
+vld1_p64_x4
+vld1_p8_x2
+vld1_p8_x3
+vld1_p8_x4
+vld1_s16_x2
+vld1_s16_x3
+vld1_s16_x4
+vld1_s32_x2
+vld1_s32_x3
+vld1_s32_x4
+vld1_s64_x2
+vld1_s64_x3
+vld1_s64_x4
+vld1_s8_x2
+vld1_s8_x3
+vld1_s8_x4
+vld1_u16_x2
+vld1_u16_x3
+vld1_u16_x4
+vld1_u32_x2
+vld1_u32_x3
+vld1_u32_x4
+vld1_u64_x2
+vld1_u64_x3
+vld1_u64_x4
+vld1_u8_x2
+vld1_u8_x3
+vld1_u8_x4
+vld1q_f16_x2
+vld1q_f16_x3
+vld1q_f16_x4
+vld1q_f32_x2
+vld1q_f32_x3
+vld1q_f32_x4
+vld1q_f64_x2
+vld1q_f64_x3
+vld1q_f64_x4
+vld1q_p16_x2
+vld1q_p16_x3
+vld1q_p16_x4
+vld1q_p64_x2
+vld1q_p64_x3
+vld1q_p64_x4
+vld1q_p8_x2
+vld1q_p8_x3
+vld1q_p8_x4
+vld1q_s16_x2
+vld1q_s16_x3
+vld1q_s16_x4
+vld1q_s32_x2
+vld1q_s32_x3
+vld1q_s32_x4
+vld1q_s64_x2
+vld1q_s64_x3
+vld1q_s64_x4
+vld1q_s8_x2
+vld1q_s8_x3
+vld1q_s8_x4
+vld1q_u16_x2
+vld1q_u16_x3
+vld1q_u16_x4
+vld1q_u32_x2
+vld1q_u32_x3
+vld1q_u32_x4
+vld1q_u64_x2
+vld1q_u64_x3
+vld1q_u64_x4
+vld1q_u8_x2
+vld1q_u8_x3
+vld1q_u8_x4
+vld2_f16
+vld2_f32
+vld2_lane_f16
+vld2_lane_f32
+vld2_lane_s16
+vld2_lane_s32
+vld2_lane_s64
+vld2_lane_s8
+vld2_lane_u16
+vld2_lane_u32
+vld2_lane_u64
+vld2_lane_u8
+vld2_p16
+vld2_p8
+vld2_s16
+vld2_s32
+vld2_s64
+vld2_s8
+vld2_u16
+vld2_u32
+vld2_u64
+vld2_u8
+vld2q_f16
+vld2q_f32
+vld2q_f64
+vld2q_lane_f16
+vld2q_lane_f32
+vld2q_lane_s16
+vld2q_lane_s32
+vld2q_lane_s64
+vld2q_lane_s8
+vld2q_lane_u16
+vld2q_lane_u32
+vld2q_lane_u64
+vld2q_lane_u8
+vld2q_p16
+vld2q_p8
+vld2q_s16
+vld2q_s32
+vld2q_s64
+vld2q_s8
+vld2q_u16
+vld2q_u32
+vld2q_u64
+vld2q_u8
+vld3_f16
+vld3_lane_f16
+vld3_lane_f32
+vld3_lane_s16
+vld3_lane_s32
+vld3_lane_s64
+vld3_lane_s8
+vld3_lane_u16
+vld3_lane_u32
+vld3_lane_u64
+vld3_lane_u8
+vld3q_f16
+vld3q_lane_f16
+vld3q_lane_f32
+vld3q_lane_s16
+vld3q_lane_s32
+vld3q_lane_s64
+vld3q_lane_s8
+vld3q_lane_u16
+vld3q_lane_u32
+vld3q_lane_u64
+vld3q_lane_u8
+vld4_f16
+vld4_lane_f16
+vld4_lane_f32
+vld4_lane_s16
+vld4_lane_s32
+vld4_lane_s64
+vld4_lane_s8
+vld4_lane_u16
+vld4_lane_u32
+vld4_lane_u64
+vld4_lane_u8
+vld4q_f16
+vld4q_lane_f16
+vld4q_lane_f32
+vld4q_lane_s16
+vld4q_lane_s32
+vld4q_lane_s64
+vld4q_lane_s8
+vld4q_lane_u16
+vld4q_lane_u32
+vld4q_lane_u64
+vld4q_lane_u8
+vqtbl2_p8
+vqtbl2_s8
+vqtbl2_u8
+vqtbl2q_p8
+vqtbl2q_s8
+vqtbl2q_u8
+vqtbl3_p8
+vqtbl3_s8
+vqtbl3_u8
+vqtbl3q_p8
+vqtbl3q_s8
+vqtbl3q_u8
+vqtbl4_p8
+vqtbl4_s8
+vqtbl4_u8
+vqtbl4q_p8
+vqtbl4q_s8
+vqtbl4q_u8
+vqtbx1_p8
+vqtbx1_s8
+vqtbx1_u8
+vqtbx1q_p8
+vqtbx1q_s8
+vqtbx1q_u8
+vqtbx2_p8
+vqtbx2_s8
+vqtbx2_u8
+vqtbx2q_p8
+vqtbx2q_s8
+vqtbx2q_u8
+vqtbx3_p8
+vqtbx3_s8
+vqtbx3_u8
+vqtbx3q_p8
+vqtbx3q_s8
+vqtbx3q_u8
+vqtbx4_p8
+vqtbx4_s8
+vqtbx4_u8
+vqtbx4q_p8
+vqtbx4q_s8
+vqtbx4q_u8
+vrhadd_s16
+vrhadd_s32
+vrhadd_s8
+vrhadd_u16
+vrhadd_u32
+vrhadd_u8
+vrhaddq_s16
+vrhaddq_s32
+vrhaddq_s8
+vrhaddq_u16
+vrhaddq_u32
+vrhaddq_u8
+vsli_n_p16
+vsli_n_p8
+vsli_n_s16
+vsli_n_s32
+vsli_n_s64
+vsli_n_s8
+vsli_n_u16
+vsli_n_u32
+vsli_n_u64
+vsli_n_u8
+vsliq_n_p16
+vsliq_n_p8
+vsliq_n_s16
+vsliq_n_s32
+vsliq_n_s64
+vsliq_n_s8
+vsliq_n_u16
+vsliq_n_u32
+vsliq_n_u64
+vsliq_n_u8
+vtbl3_p8
+vtbl3_s8
+vtbl3_u8
+vtbl4_p8
+vtbl4_s8
+vtbl4_u8
+vtbx1_p8
+vtbx1_s8
+vtbx1_u8
+vtbx2_p8
+vtbx2_s8
+vtbx2_u8
+vtbx3_p8
+vtbx3_s8
+vtbx3_u8
+vtbx4_p8
+vtbx4_s8
+vtbx4_u8