Couple of clippy fixes

Author: bjorn3

src/abi/mod.rs

@@ -322,23 +322,22 @@ pub(crate) fn codegen_fn_prelude<'tcx>(fx: &mut FunctionCx<'_, '_, 'tcx>, start_
         // not mutated by the current function, this is necessary to support unsized arguments.
         if let ArgKind::Normal(Some(ArgValue { value: val, is_underaligned_pointee: false })) =
             arg_kind
+            && let Some((addr, meta)) = val.try_to_ptr()
         {
-            if let Some((addr, meta)) = val.try_to_ptr() {
-                // Ownership of the value at the backing storage for an argument is passed to the
-                // callee per the ABI, so it is fine to borrow the backing storage of this argument
-                // to prevent a copy.
+            // Ownership of the value at the backing storage for an argument is passed to the
+            // callee per the ABI, so it is fine to borrow the backing storage of this argument
+            // to prevent a copy.
 
-                let place = if let Some(meta) = meta {
-                    CPlace::for_ptr_with_extra(addr, meta, val.layout())
-                } else {
-                    CPlace::for_ptr(addr, val.layout())
-                };
+            let place = if let Some(meta) = meta {
+                CPlace::for_ptr_with_extra(addr, meta, val.layout())
+            } else {
+                CPlace::for_ptr(addr, val.layout())
+            };
 
-                self::comments::add_local_place_comments(fx, place, local);
+            self::comments::add_local_place_comments(fx, place, local);
 
-                assert_eq!(fx.local_map.push(place), local);
-                continue;
-            }
+            assert_eq!(fx.local_map.push(place), local);
+            continue;
         }
 
         let layout = fx.layout_of(ty);

src/analyze.rs

@@ -23,14 +23,10 @@ pub(crate) fn analyze(fx: &FunctionCx<'_, '_, '_>) -> IndexVec<Local, SsaKind> {
 
     for bb in fx.mir.basic_blocks.iter() {
         for stmt in bb.statements.iter() {
-            match &stmt.kind {
-                Assign(place_and_rval) => match &place_and_rval.1 {
-                    Rvalue::Ref(_, _, place) | Rvalue::RawPtr(_, place) => {
-                        flag_map[place.local] = SsaKind::NotSsa;
-                    }
-                    _ => {}
-                },
-                _ => {}
+            if let Assign(place_and_rval) = &stmt.kind
+                && let Rvalue::Ref(_, _, place) | Rvalue::RawPtr(_, place) = &place_and_rval.1
+            {
+                flag_map[place.local] = SsaKind::NotSsa;
             }
         }
     }

src/base.rs

@@ -1047,7 +1047,7 @@ pub(crate) fn codegen_operand<'tcx>(
         Operand::RuntimeChecks(checks) => {
             let val = checks.value(fx.tcx.sess);
             let layout = fx.layout_of(fx.tcx.types.bool);
-            return CValue::const_val(fx, layout, val.into());
+            CValue::const_val(fx, layout, val.into())
         }
     }
 }

src/inline_asm.rs

@@ -424,13 +424,10 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
 
         // Allocate stack slots for inout
         for (i, operand) in self.operands.iter().enumerate() {
-            match *operand {
-                CInlineAsmOperand::InOut { reg, out_place: Some(_), .. } => {
-                    let slot = new_slot(reg.reg_class());
-                    slots_input[i] = Some(slot);
-                    slots_output[i] = Some(slot);
-                }
-                _ => (),
+            if let CInlineAsmOperand::InOut { reg, out_place: Some(_), .. } = *operand {
+                let slot = new_slot(reg.reg_class());
+                slots_input[i] = Some(slot);
+                slots_output[i] = Some(slot);
             }
         }
 
@@ -456,11 +453,8 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
 
         // Allocate stack slots for output
         for (i, operand) in self.operands.iter().enumerate() {
-            match *operand {
-                CInlineAsmOperand::Out { reg, place: Some(_), .. } => {
-                    slots_output[i] = Some(new_slot(reg.reg_class()));
-                }
-                _ => (),
+            if let CInlineAsmOperand::Out { reg, place: Some(_), .. } = *operand {
+                slots_output[i] = Some(new_slot(reg.reg_class()));
             }
         }
 

src/intrinsics/simd.rs

@@ -371,7 +371,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
             }
 
             for i in 0..lane_count {
-                let ret_lane = ret.place_lane(fx, i.into());
+                let ret_lane = ret.place_lane(fx, i);
                 ret_lane.write_cvalue(fx, value);
             }
         }

src/value_and_place.rs

@@ -686,17 +686,14 @@ impl<'tcx> CPlace<'tcx> {
     ) -> CPlace<'tcx> {
         let layout = self.layout();
 
-        match self.inner {
-            CPlaceInner::VarPair(local, var1, var2) => {
-                let layout = layout.field(&*fx, field.index());
+        if let CPlaceInner::VarPair(local, var1, var2) = self.inner {
+            let layout = layout.field(&*fx, field.index());
 
-                match field.as_u32() {
-                    0 => return CPlace { inner: CPlaceInner::Var(local, var1), layout },
-                    1 => return CPlace { inner: CPlaceInner::Var(local, var2), layout },
-                    _ => unreachable!("field should be 0 or 1"),
-                }
+            match field.as_u32() {
+                0 => return CPlace { inner: CPlaceInner::Var(local, var1), layout },
+                1 => return CPlace { inner: CPlaceInner::Var(local, var2), layout },
+                _ => unreachable!("field should be 0 or 1"),
             }
-            _ => {}
         }
 
         let (base, extra) = match self.inner {