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adamgemmelladamgemmell
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Revert "Split vcopyq_lane{q}_p64 due to vsetq_lane_p64 requiring aes"
This reverts commit 2ada72b.
1 parent 1662138 commit 3c627f5

2 files changed

Lines changed: 229 additions & 90 deletions

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‎crates/core_arch/src/aarch64/neon/generated.rs‎

Lines changed: 227 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -4813,6 +4813,7 @@ pub fn vcopy_lane_p64<const LANE1: i32, const LANE2: i32>(
48134813
#[doc = "Insert vector element from another vector element"]
48144814
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"]
48154815
#[inline]
4816+
#[cfg(target_endian = "little")]
48164817
#[target_feature(enable = "neon")]
48174818
#[cfg_attr(
48184819
all(test, target_endian = "little"),
@@ -4829,8 +4830,33 @@ pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
48294830
vset_lane_f32::<LANE1>(vgetq_lane_f32::<LANE2>(b), a)
48304831
}
48314832
#[doc = "Insert vector element from another vector element"]
4833+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"]
4834+
#[inline]
4835+
#[cfg(target_endian = "big")]
4836+
#[target_feature(enable = "neon")]
4837+
#[cfg_attr(
4838+
all(test, target_endian = "little"),
4839+
assert_instr(mov, LANE1 = 0, LANE2 = 0)
4840+
)]
4841+
#[rustc_legacy_const_generics(1, 3)]
4842+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4843+
pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
4844+
a: float32x2_t,
4845+
b: float32x4_t,
4846+
) -> float32x2_t {
4847+
static_assert_uimm_bits!(LANE1, 1);
4848+
static_assert_uimm_bits!(LANE2, 2);
4849+
unsafe {
4850+
let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
4851+
let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
4852+
let ret_val: float32x2_t = vset_lane_f32::<LANE1>(vgetq_lane_f32::<LANE2>(b), a);
4853+
simd_shuffle!(ret_val, ret_val, [1, 0])
4854+
}
4855+
}
4856+
#[doc = "Insert vector element from another vector element"]
48324857
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"]
48334858
#[inline]
4859+
#[cfg(target_endian = "little")]
48344860
#[target_feature(enable = "neon")]
48354861
#[cfg_attr(
48364862
all(test, target_endian = "little"),
@@ -4844,8 +4870,31 @@ pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x1
48444870
vset_lane_s8::<LANE1>(vgetq_lane_s8::<LANE2>(b), a)
48454871
}
48464872
#[doc = "Insert vector element from another vector element"]
4873+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"]
4874+
#[inline]
4875+
#[cfg(target_endian = "big")]
4876+
#[target_feature(enable = "neon")]
4877+
#[cfg_attr(
4878+
all(test, target_endian = "little"),
4879+
assert_instr(mov, LANE1 = 0, LANE2 = 0)
4880+
)]
4881+
#[rustc_legacy_const_generics(1, 3)]
4882+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4883+
pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x16_t) -> int8x8_t {
4884+
static_assert_uimm_bits!(LANE1, 3);
4885+
static_assert_uimm_bits!(LANE2, 4);
4886+
unsafe {
4887+
let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
4888+
let b: int8x16_t =
4889+
simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
4890+
let ret_val: int8x8_t = vset_lane_s8::<LANE1>(vgetq_lane_s8::<LANE2>(b), a);
4891+
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
4892+
}
4893+
}
4894+
#[doc = "Insert vector element from another vector element"]
48474895
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"]
48484896
#[inline]
4897+
#[cfg(target_endian = "little")]
48494898
#[target_feature(enable = "neon")]
48504899
#[cfg_attr(
48514900
all(test, target_endian = "little"),
@@ -4862,8 +4911,33 @@ pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
48624911
vset_lane_s16::<LANE1>(vgetq_lane_s16::<LANE2>(b), a)
48634912
}
48644913
#[doc = "Insert vector element from another vector element"]
4914+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"]
4915+
#[inline]
4916+
#[cfg(target_endian = "big")]
4917+
#[target_feature(enable = "neon")]
4918+
#[cfg_attr(
4919+
all(test, target_endian = "little"),
4920+
assert_instr(mov, LANE1 = 0, LANE2 = 0)
4921+
)]
4922+
#[rustc_legacy_const_generics(1, 3)]
4923+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4924+
pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
4925+
a: int16x4_t,
4926+
b: int16x8_t,
4927+
) -> int16x4_t {
4928+
static_assert_uimm_bits!(LANE1, 2);
4929+
static_assert_uimm_bits!(LANE2, 3);
4930+
unsafe {
4931+
let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
4932+
let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
4933+
let ret_val: int16x4_t = vset_lane_s16::<LANE1>(vgetq_lane_s16::<LANE2>(b), a);
4934+
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
4935+
}
4936+
}
4937+
#[doc = "Insert vector element from another vector element"]
48654938
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"]
48664939
#[inline]
4940+
#[cfg(target_endian = "little")]
48674941
#[target_feature(enable = "neon")]
48684942
#[cfg_attr(
48694943
all(test, target_endian = "little"),
@@ -4880,8 +4954,33 @@ pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
48804954
vset_lane_s32::<LANE1>(vgetq_lane_s32::<LANE2>(b), a)
48814955
}
48824956
#[doc = "Insert vector element from another vector element"]
4957+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"]
4958+
#[inline]
4959+
#[cfg(target_endian = "big")]
4960+
#[target_feature(enable = "neon")]
4961+
#[cfg_attr(
4962+
all(test, target_endian = "little"),
4963+
assert_instr(mov, LANE1 = 0, LANE2 = 0)
4964+
)]
4965+
#[rustc_legacy_const_generics(1, 3)]
4966+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4967+
pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
4968+
a: int32x2_t,
4969+
b: int32x4_t,
4970+
) -> int32x2_t {
4971+
static_assert_uimm_bits!(LANE1, 1);
4972+
static_assert_uimm_bits!(LANE2, 2);
4973+
unsafe {
4974+
let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
4975+
let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
4976+
let ret_val: int32x2_t = vset_lane_s32::<LANE1>(vgetq_lane_s32::<LANE2>(b), a);
4977+
simd_shuffle!(ret_val, ret_val, [1, 0])
4978+
}
4979+
}
4980+
#[doc = "Insert vector element from another vector element"]
48834981
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"]
48844982
#[inline]
4983+
#[cfg(target_endian = "little")]
48854984
#[target_feature(enable = "neon")]
48864985
#[cfg_attr(
48874986
all(test, target_endian = "little"),
@@ -4898,8 +4997,34 @@ pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
48984997
vset_lane_u8::<LANE1>(vgetq_lane_u8::<LANE2>(b), a)
48994998
}
49004999
#[doc = "Insert vector element from another vector element"]
5000+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"]
5001+
#[inline]
5002+
#[cfg(target_endian = "big")]
5003+
#[target_feature(enable = "neon")]
5004+
#[cfg_attr(
5005+
all(test, target_endian = "little"),
5006+
assert_instr(mov, LANE1 = 0, LANE2 = 0)
5007+
)]
5008+
#[rustc_legacy_const_generics(1, 3)]
5009+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5010+
pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
5011+
a: uint8x8_t,
5012+
b: uint8x16_t,
5013+
) -> uint8x8_t {
5014+
static_assert_uimm_bits!(LANE1, 3);
5015+
static_assert_uimm_bits!(LANE2, 4);
5016+
unsafe {
5017+
let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
5018+
let b: uint8x16_t =
5019+
simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
5020+
let ret_val: uint8x8_t = vset_lane_u8::<LANE1>(vgetq_lane_u8::<LANE2>(b), a);
5021+
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
5022+
}
5023+
}
5024+
#[doc = "Insert vector element from another vector element"]
49015025
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"]
49025026
#[inline]
5027+
#[cfg(target_endian = "little")]
49035028
#[target_feature(enable = "neon")]
49045029
#[cfg_attr(
49055030
all(test, target_endian = "little"),
@@ -4916,8 +5041,33 @@ pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
49165041
vset_lane_u16::<LANE1>(vgetq_lane_u16::<LANE2>(b), a)
49175042
}
49185043
#[doc = "Insert vector element from another vector element"]
5044+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"]
5045+
#[inline]
5046+
#[cfg(target_endian = "big")]
5047+
#[target_feature(enable = "neon")]
5048+
#[cfg_attr(
5049+
all(test, target_endian = "little"),
5050+
assert_instr(mov, LANE1 = 0, LANE2 = 0)
5051+
)]
5052+
#[rustc_legacy_const_generics(1, 3)]
5053+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5054+
pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
5055+
a: uint16x4_t,
5056+
b: uint16x8_t,
5057+
) -> uint16x4_t {
5058+
static_assert_uimm_bits!(LANE1, 2);
5059+
static_assert_uimm_bits!(LANE2, 3);
5060+
unsafe {
5061+
let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
5062+
let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
5063+
let ret_val: uint16x4_t = vset_lane_u16::<LANE1>(vgetq_lane_u16::<LANE2>(b), a);
5064+
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
5065+
}
5066+
}
5067+
#[doc = "Insert vector element from another vector element"]
49195068
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"]
49205069
#[inline]
5070+
#[cfg(target_endian = "little")]
49215071
#[target_feature(enable = "neon")]
49225072
#[cfg_attr(
49235073
all(test, target_endian = "little"),
@@ -4934,8 +5084,33 @@ pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
49345084
vset_lane_u32::<LANE1>(vgetq_lane_u32::<LANE2>(b), a)
49355085
}
49365086
#[doc = "Insert vector element from another vector element"]
5087+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"]
5088+
#[inline]
5089+
#[cfg(target_endian = "big")]
5090+
#[target_feature(enable = "neon")]
5091+
#[cfg_attr(
5092+
all(test, target_endian = "little"),
5093+
assert_instr(mov, LANE1 = 0, LANE2 = 0)
5094+
)]
5095+
#[rustc_legacy_const_generics(1, 3)]
5096+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5097+
pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
5098+
a: uint32x2_t,
5099+
b: uint32x4_t,
5100+
) -> uint32x2_t {
5101+
static_assert_uimm_bits!(LANE1, 1);
5102+
static_assert_uimm_bits!(LANE2, 2);
5103+
unsafe {
5104+
let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
5105+
let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
5106+
let ret_val: uint32x2_t = vset_lane_u32::<LANE1>(vgetq_lane_u32::<LANE2>(b), a);
5107+
simd_shuffle!(ret_val, ret_val, [1, 0])
5108+
}
5109+
}
5110+
#[doc = "Insert vector element from another vector element"]
49375111
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"]
49385112
#[inline]
5113+
#[cfg(target_endian = "little")]
49395114
#[target_feature(enable = "neon")]
49405115
#[cfg_attr(
49415116
all(test, target_endian = "little"),
@@ -4952,8 +5127,34 @@ pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
49525127
vset_lane_p8::<LANE1>(vgetq_lane_p8::<LANE2>(b), a)
49535128
}
49545129
#[doc = "Insert vector element from another vector element"]
5130+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"]
5131+
#[inline]
5132+
#[cfg(target_endian = "big")]
5133+
#[target_feature(enable = "neon")]
5134+
#[cfg_attr(
5135+
all(test, target_endian = "little"),
5136+
assert_instr(mov, LANE1 = 0, LANE2 = 0)
5137+
)]
5138+
#[rustc_legacy_const_generics(1, 3)]
5139+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5140+
pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
5141+
a: poly8x8_t,
5142+
b: poly8x16_t,
5143+
) -> poly8x8_t {
5144+
static_assert_uimm_bits!(LANE1, 3);
5145+
static_assert_uimm_bits!(LANE2, 4);
5146+
unsafe {
5147+
let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
5148+
let b: poly8x16_t =
5149+
simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
5150+
let ret_val: poly8x8_t = vset_lane_p8::<LANE1>(vgetq_lane_p8::<LANE2>(b), a);
5151+
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
5152+
}
5153+
}
5154+
#[doc = "Insert vector element from another vector element"]
49555155
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"]
49565156
#[inline]
5157+
#[cfg(target_endian = "little")]
49575158
#[target_feature(enable = "neon")]
49585159
#[cfg_attr(
49595160
all(test, target_endian = "little"),
@@ -4970,6 +5171,30 @@ pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
49705171
vset_lane_p16::<LANE1>(vgetq_lane_p16::<LANE2>(b), a)
49715172
}
49725173
#[doc = "Insert vector element from another vector element"]
5174+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"]
5175+
#[inline]
5176+
#[cfg(target_endian = "big")]
5177+
#[target_feature(enable = "neon")]
5178+
#[cfg_attr(
5179+
all(test, target_endian = "little"),
5180+
assert_instr(mov, LANE1 = 0, LANE2 = 0)
5181+
)]
5182+
#[rustc_legacy_const_generics(1, 3)]
5183+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5184+
pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
5185+
a: poly16x4_t,
5186+
b: poly16x8_t,
5187+
) -> poly16x4_t {
5188+
static_assert_uimm_bits!(LANE1, 2);
5189+
static_assert_uimm_bits!(LANE2, 3);
5190+
unsafe {
5191+
let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
5192+
let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
5193+
let ret_val: poly16x4_t = vset_lane_p16::<LANE1>(vgetq_lane_p16::<LANE2>(b), a);
5194+
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
5195+
}
5196+
}
5197+
#[doc = "Insert vector element from another vector element"]
49735198
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f64)"]
49745199
#[inline]
49755200
#[target_feature(enable = "neon")]
@@ -5104,7 +5329,6 @@ pub fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(
51045329
#[doc = "Insert vector element from another vector element"]
51055330
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"]
51065331
#[inline]
5107-
#[cfg(target_endian = "little")]
51085332
#[target_feature(enable = "neon")]
51095333
#[cfg_attr(
51105334
all(test, target_endian = "little"),
@@ -5119,32 +5343,7 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
51195343
static_assert_uimm_bits!(LANE1, 1);
51205344
static_assert!(LANE2 == 0);
51215345
let b: poly64x2_t = vcombine_p64(b, b);
5122-
unsafe { simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)) }
5123-
}
5124-
#[doc = "Insert vector element from another vector element"]
5125-
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"]
5126-
#[inline]
5127-
#[cfg(target_endian = "big")]
5128-
#[target_feature(enable = "neon")]
5129-
#[cfg_attr(
5130-
all(test, target_endian = "little"),
5131-
assert_instr(mov, LANE1 = 1, LANE2 = 0)
5132-
)]
5133-
#[rustc_legacy_const_generics(1, 3)]
5134-
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5135-
pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
5136-
a: poly64x2_t,
5137-
b: poly64x1_t,
5138-
) -> poly64x2_t {
5139-
static_assert_uimm_bits!(LANE1, 1);
5140-
static_assert!(LANE2 == 0);
5141-
unsafe {
5142-
let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
5143-
let b: poly64x2_t = vcombine_p64(b, b);
5144-
let ret_val: poly64x2_t =
5145-
simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64));
5146-
simd_shuffle!(ret_val, ret_val, [1, 0])
5147-
}
5346+
vsetq_lane_p64::<LANE1>(vgetq_lane_p64::<LANE2>(b), a)
51485347
}
51495348
#[doc = "Insert vector element from another vector element"]
51505349
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"]
@@ -5514,26 +5713,6 @@ pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
55145713
#[doc = "Insert vector element from another vector element"]
55155714
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
55165715
#[inline]
5517-
#[cfg(target_endian = "little")]
5518-
#[target_feature(enable = "neon")]
5519-
#[cfg_attr(
5520-
all(test, target_endian = "little"),
5521-
assert_instr(mov, LANE1 = 0, LANE2 = 0)
5522-
)]
5523-
#[rustc_legacy_const_generics(1, 3)]
5524-
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5525-
pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
5526-
a: poly64x2_t,
5527-
b: poly64x2_t,
5528-
) -> poly64x2_t {
5529-
static_assert_uimm_bits!(LANE1, 1);
5530-
static_assert_uimm_bits!(LANE2, 1);
5531-
unsafe { simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)) }
5532-
}
5533-
#[doc = "Insert vector element from another vector element"]
5534-
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
5535-
#[inline]
5536-
#[cfg(target_endian = "big")]
55375716
#[target_feature(enable = "neon")]
55385717
#[cfg_attr(
55395718
all(test, target_endian = "little"),
@@ -5547,13 +5726,7 @@ pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
55475726
) -> poly64x2_t {
55485727
static_assert_uimm_bits!(LANE1, 1);
55495728
static_assert_uimm_bits!(LANE2, 1);
5550-
unsafe {
5551-
let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
5552-
let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]);
5553-
let ret_val: poly64x2_t =
5554-
simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64));
5555-
simd_shuffle!(ret_val, ret_val, [1, 0])
5556-
}
5729+
vsetq_lane_p64::<LANE1>(vgetq_lane_p64::<LANE2>(b), a)
55575730
}
55585731
#[doc = "Insert vector element from another vector element"]
55595732
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"]

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