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sayantnsayantn
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Disable some assert_instr tests in big-endian
1 parent 978d6b4 commit d8f77a2

2 files changed

Lines changed: 17 additions & 17 deletions

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‎crates/core_arch/src/aarch64/neon/generated.rs‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -9852,7 +9852,7 @@ pub fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
98529852
#[cfg(target_endian = "little")]
98539853
#[target_feature(enable = "neon")]
98549854
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9855-
#[cfg_attr(test, assert_instr(fmov))]
9855+
#[cfg_attr(test, assert_instr(nop))]
98569856
pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
98579857
unsafe { float64x1_t([simd_extract!(a, 1)]) }
98589858
}
@@ -9862,7 +9862,7 @@ pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
98629862
#[cfg(target_endian = "big")]
98639863
#[target_feature(enable = "neon")]
98649864
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9865-
#[cfg_attr(test, assert_instr(fmov))]
9865+
#[cfg_attr(test, assert_instr(nop))]
98669866
pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
98679867
unsafe {
98689868
let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
@@ -16356,7 +16356,7 @@ pub fn vqdmlal_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t)
1635616356
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_lane_s16)"]
1635716357
#[inline]
1635816358
#[target_feature(enable = "neon")]
16359-
#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
16359+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))]
1636016360
#[rustc_legacy_const_generics(3)]
1636116361
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1636216362
pub fn vqdmlalh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
@@ -16367,7 +16367,7 @@ pub fn vqdmlalh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
1636716367
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16)"]
1636816368
#[inline]
1636916369
#[target_feature(enable = "neon")]
16370-
#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
16370+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))]
1637116371
#[rustc_legacy_const_generics(3)]
1637216372
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1637316373
pub fn vqdmlalh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32 {
@@ -16378,7 +16378,7 @@ pub fn vqdmlalh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32
1637816378
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32)"]
1637916379
#[inline]
1638016380
#[target_feature(enable = "neon")]
16381-
#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
16381+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))]
1638216382
#[rustc_legacy_const_generics(3)]
1638316383
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1638416384
pub fn vqdmlals_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
@@ -16389,7 +16389,7 @@ pub fn vqdmlals_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
1638916389
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32)"]
1639016390
#[inline]
1639116391
#[target_feature(enable = "neon")]
16392-
#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
16392+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))]
1639316393
#[rustc_legacy_const_generics(3)]
1639416394
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1639516395
pub fn vqdmlals_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64 {
@@ -16400,7 +16400,7 @@ pub fn vqdmlals_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64
1640016400
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16)"]
1640116401
#[inline]
1640216402
#[target_feature(enable = "neon")]
16403-
#[cfg_attr(test, assert_instr(sqdmlal))]
16403+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal))]
1640416404
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1640516405
pub fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 {
1640616406
let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c));
@@ -16522,7 +16522,7 @@ pub fn vqdmlsl_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t)
1652216522
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_lane_s16)"]
1652316523
#[inline]
1652416524
#[target_feature(enable = "neon")]
16525-
#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
16525+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))]
1652616526
#[rustc_legacy_const_generics(3)]
1652716527
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1652816528
pub fn vqdmlslh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
@@ -16533,7 +16533,7 @@ pub fn vqdmlslh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
1653316533
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16)"]
1653416534
#[inline]
1653516535
#[target_feature(enable = "neon")]
16536-
#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
16536+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))]
1653716537
#[rustc_legacy_const_generics(3)]
1653816538
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1653916539
pub fn vqdmlslh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32 {
@@ -16544,7 +16544,7 @@ pub fn vqdmlslh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32
1654416544
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32)"]
1654516545
#[inline]
1654616546
#[target_feature(enable = "neon")]
16547-
#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
16547+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))]
1654816548
#[rustc_legacy_const_generics(3)]
1654916549
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1655016550
pub fn vqdmlsls_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
@@ -16555,7 +16555,7 @@ pub fn vqdmlsls_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
1655516555
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32)"]
1655616556
#[inline]
1655716557
#[target_feature(enable = "neon")]
16558-
#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
16558+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))]
1655916559
#[rustc_legacy_const_generics(3)]
1656016560
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1656116561
pub fn vqdmlsls_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64 {
@@ -16566,7 +16566,7 @@ pub fn vqdmlsls_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64
1656616566
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16)"]
1656716567
#[inline]
1656816568
#[target_feature(enable = "neon")]
16569-
#[cfg_attr(test, assert_instr(sqdmlsl))]
16569+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl))]
1657016570
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1657116571
pub fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 {
1657216572
let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c));

‎crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7083,7 +7083,7 @@ intrinsics:
70837083
arguments: ["a: {type[0]}", "b: {type[1]}", "c: {type[1]}"]
70847084
return_type: "{type[0]}"
70857085
attr:
7086-
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal]]}]]
7086+
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal]]}]]
70877087
- *neon-stable
70887088
safety: safe
70897089
types:
@@ -7111,7 +7111,7 @@ intrinsics:
71117111
arguments: ["a: {type[0]}", "b: {type[1]}", "c: {neon_type[2]}"]
71127112
return_type: "{type[0]}"
71137113
attr:
7114-
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'LANE = 0']]}]]
7114+
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal, 'LANE = 0']]}]]
71157115
- FnCall: [rustc_legacy_const_generics, ['3']]
71167116
- *neon-stable
71177117
static_defs: ['const LANE: i32']
@@ -7197,7 +7197,7 @@ intrinsics:
71977197
arguments: ["a: {type[0]}", "b: {type[1]}", "c: {type[1]}"]
71987198
return_type: "{type[0]}"
71997199
attr:
7200-
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl]]}]]
7200+
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl]]}]]
72017201
- *neon-stable
72027202
safety: safe
72037203
types:
@@ -7225,7 +7225,7 @@ intrinsics:
72257225
arguments: ["a: {type[0]}", "b: {type[1]}", "c: {neon_type[2]}"]
72267226
return_type: "{type[0]}"
72277227
attr:
7228-
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'LANE = 0']]}]]
7228+
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'LANE = 0']]}]]
72297229
- FnCall: [rustc_legacy_const_generics, ['3']]
72307230
- *neon-stable
72317231
static_defs: ['const LANE: i32']
@@ -14186,7 +14186,7 @@ intrinsics:
1418614186
safety: safe
1418714187
big_endian_inverse: true
1418814188
types:
14189-
- ['vget_high_f64', 'float64x2_t', 'float64x1_t', 'fmov', 'float64x1_t([simd_extract!(a, 1)])']
14189+
- ['vget_high_f64', 'float64x2_t', 'float64x1_t', 'nop', 'float64x1_t([simd_extract!(a, 1)])']
1419014190
- ['vget_low_f64', 'float64x2_t', 'float64x1_t', 'nop', 'float64x1_t([simd_extract!(a, 0)])']
1419114191
compose:
1419214192
- Identifier: ['{type[4]}', UnsafeSymbol]

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