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sayantnsayantn
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Disable some assert_instr tests in big-endian
1 parent eb471db commit de4895d

2 files changed

Lines changed: 17 additions & 17 deletions

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‎crates/core_arch/src/aarch64/neon/generated.rs‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -10499,7 +10499,7 @@ pub fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
1049910499
#[cfg(target_endian = "little")]
1050010500
#[target_feature(enable = "neon")]
1050110501
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10502-
#[cfg_attr(test, assert_instr(fmov))]
10502+
#[cfg_attr(test, assert_instr(nop))]
1050310503
pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
1050410504
unsafe { float64x1_t([simd_extract!(a, 1)]) }
1050510505
}
@@ -10509,7 +10509,7 @@ pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
1050910509
#[cfg(target_endian = "big")]
1051010510
#[target_feature(enable = "neon")]
1051110511
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10512-
#[cfg_attr(test, assert_instr(fmov))]
10512+
#[cfg_attr(test, assert_instr(nop))]
1051310513
pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
1051410514
unsafe {
1051510515
let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
@@ -17003,7 +17003,7 @@ pub fn vqdmlal_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t)
1700317003
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_lane_s16)"]
1700417004
#[inline]
1700517005
#[target_feature(enable = "neon")]
17006-
#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
17006+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))]
1700717007
#[rustc_legacy_const_generics(3)]
1700817008
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1700917009
pub fn vqdmlalh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
@@ -17014,7 +17014,7 @@ pub fn vqdmlalh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
1701417014
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16)"]
1701517015
#[inline]
1701617016
#[target_feature(enable = "neon")]
17017-
#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
17017+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))]
1701817018
#[rustc_legacy_const_generics(3)]
1701917019
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1702017020
pub fn vqdmlalh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32 {
@@ -17025,7 +17025,7 @@ pub fn vqdmlalh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32
1702517025
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32)"]
1702617026
#[inline]
1702717027
#[target_feature(enable = "neon")]
17028-
#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
17028+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))]
1702917029
#[rustc_legacy_const_generics(3)]
1703017030
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1703117031
pub fn vqdmlals_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
@@ -17036,7 +17036,7 @@ pub fn vqdmlals_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
1703617036
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32)"]
1703717037
#[inline]
1703817038
#[target_feature(enable = "neon")]
17039-
#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
17039+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))]
1704017040
#[rustc_legacy_const_generics(3)]
1704117041
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1704217042
pub fn vqdmlals_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64 {
@@ -17047,7 +17047,7 @@ pub fn vqdmlals_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64
1704717047
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16)"]
1704817048
#[inline]
1704917049
#[target_feature(enable = "neon")]
17050-
#[cfg_attr(test, assert_instr(sqdmlal))]
17050+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal))]
1705117051
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1705217052
pub fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 {
1705317053
let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c));
@@ -17169,7 +17169,7 @@ pub fn vqdmlsl_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t)
1716917169
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_lane_s16)"]
1717017170
#[inline]
1717117171
#[target_feature(enable = "neon")]
17172-
#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
17172+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))]
1717317173
#[rustc_legacy_const_generics(3)]
1717417174
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1717517175
pub fn vqdmlslh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
@@ -17180,7 +17180,7 @@ pub fn vqdmlslh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
1718017180
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16)"]
1718117181
#[inline]
1718217182
#[target_feature(enable = "neon")]
17183-
#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
17183+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))]
1718417184
#[rustc_legacy_const_generics(3)]
1718517185
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1718617186
pub fn vqdmlslh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32 {
@@ -17191,7 +17191,7 @@ pub fn vqdmlslh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32
1719117191
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32)"]
1719217192
#[inline]
1719317193
#[target_feature(enable = "neon")]
17194-
#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
17194+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))]
1719517195
#[rustc_legacy_const_generics(3)]
1719617196
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1719717197
pub fn vqdmlsls_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
@@ -17202,7 +17202,7 @@ pub fn vqdmlsls_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
1720217202
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32)"]
1720317203
#[inline]
1720417204
#[target_feature(enable = "neon")]
17205-
#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
17205+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))]
1720617206
#[rustc_legacy_const_generics(3)]
1720717207
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1720817208
pub fn vqdmlsls_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64 {
@@ -17213,7 +17213,7 @@ pub fn vqdmlsls_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64
1721317213
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16)"]
1721417214
#[inline]
1721517215
#[target_feature(enable = "neon")]
17216-
#[cfg_attr(test, assert_instr(sqdmlsl))]
17216+
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl))]
1721717217
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1721817218
pub fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 {
1721917219
let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c));

‎crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7286,7 +7286,7 @@ intrinsics:
72867286
arguments: ["a: {type[0]}", "b: {type[1]}", "c: {type[1]}"]
72877287
return_type: "{type[0]}"
72887288
attr:
7289-
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal]]}]]
7289+
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal]]}]]
72907290
- *neon-stable
72917291
safety: safe
72927292
types:
@@ -7314,7 +7314,7 @@ intrinsics:
73147314
arguments: ["a: {type[0]}", "b: {type[1]}", "c: {neon_type[2]}"]
73157315
return_type: "{type[0]}"
73167316
attr:
7317-
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'LANE = 0']]}]]
7317+
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal, 'LANE = 0']]}]]
73187318
- FnCall: [rustc_legacy_const_generics, ['3']]
73197319
- *neon-stable
73207320
static_defs: ['const LANE: i32']
@@ -7400,7 +7400,7 @@ intrinsics:
74007400
arguments: ["a: {type[0]}", "b: {type[1]}", "c: {type[1]}"]
74017401
return_type: "{type[0]}"
74027402
attr:
7403-
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl]]}]]
7403+
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl]]}]]
74047404
- *neon-stable
74057405
safety: safe
74067406
types:
@@ -7428,7 +7428,7 @@ intrinsics:
74287428
arguments: ["a: {type[0]}", "b: {type[1]}", "c: {neon_type[2]}"]
74297429
return_type: "{type[0]}"
74307430
attr:
7431-
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'LANE = 0']]}]]
7431+
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'LANE = 0']]}]]
74327432
- FnCall: [rustc_legacy_const_generics, ['3']]
74337433
- *neon-stable
74347434
static_defs: ['const LANE: i32']
@@ -14389,7 +14389,7 @@ intrinsics:
1438914389
safety: safe
1439014390
big_endian_inverse: true
1439114391
types:
14392-
- ['vget_high_f64', 'float64x2_t', 'float64x1_t', 'fmov', 'float64x1_t([simd_extract!(a, 1)])']
14392+
- ['vget_high_f64', 'float64x2_t', 'float64x1_t', 'nop', 'float64x1_t([simd_extract!(a, 1)])']
1439314393
- ['vget_low_f64', 'float64x2_t', 'float64x1_t', 'nop', 'float64x1_t([simd_extract!(a, 0)])']
1439414394
compose:
1439514395
- Identifier: ['{type[4]}', UnsafeSymbol]

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