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AmanieuAmanieu
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Merge pull request #2100 from sayantn/gen-arm-ports
Porting some intrinsics to stdarch-gen-arm
2 parents aa5f00a + efc35fe commit f0a39a7

7 files changed

Lines changed: 409 additions & 863 deletions

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‎crates/core_arch/src/aarch64/neon/generated.rs‎

Lines changed: 158 additions & 0 deletions
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@@ -4106,6 +4106,15 @@ pub fn vcmlaq_rot90_laneq_f32<const LANE: i32>(
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vcmlaq_rot90_f32(a, b, c)
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}
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}
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#[doc = "Join two smaller vectors into a single larger vector"]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f64)"]
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#[inline]
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#[target_feature(enable = "neon")]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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#[cfg_attr(test, assert_instr(mov))]
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pub fn vcombine_f64(a: float64x1_t, b: float64x1_t) -> float64x2_t {
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unsafe { simd_shuffle!(a, b, [0, 1]) }
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}
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#[doc = "Insert vector element from another vector element"]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"]
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#[inline]
@@ -4332,6 +4341,66 @@ pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
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}
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}
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#[doc = "Insert vector element from another vector element"]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f64)"]
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))]
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#[rustc_legacy_const_generics(1, 3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub fn vcopy_lane_f64<const LANE1: i32, const LANE2: i32>(
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_a: float64x1_t,
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b: float64x1_t,
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) -> float64x1_t {
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static_assert!(LANE1 == 0);
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static_assert!(LANE2 == 0);
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b
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}
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#[doc = "Insert vector element from another vector element"]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s64)"]
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))]
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#[rustc_legacy_const_generics(1, 3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub fn vcopy_lane_s64<const LANE1: i32, const LANE2: i32>(
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_a: int64x1_t,
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b: int64x1_t,
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) -> int64x1_t {
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static_assert!(LANE1 == 0);
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static_assert!(LANE2 == 0);
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b
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}
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#[doc = "Insert vector element from another vector element"]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u64)"]
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))]
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#[rustc_legacy_const_generics(1, 3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub fn vcopy_lane_u64<const LANE1: i32, const LANE2: i32>(
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_a: uint64x1_t,
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b: uint64x1_t,
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) -> uint64x1_t {
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static_assert!(LANE1 == 0);
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static_assert!(LANE2 == 0);
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b
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}
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#[doc = "Insert vector element from another vector element"]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p64)"]
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))]
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#[rustc_legacy_const_generics(1, 3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub fn vcopy_lane_p64<const LANE1: i32, const LANE2: i32>(
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_a: poly64x1_t,
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b: poly64x1_t,
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) -> poly64x1_t {
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static_assert!(LANE1 == 0);
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static_assert!(LANE2 == 0);
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b
4402+
}
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#[doc = "Insert vector element from another vector element"]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"]
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#[inline]
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#[target_feature(enable = "neon")]
@@ -4581,6 +4650,66 @@ pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
45814650
}
45824651
}
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#[doc = "Insert vector element from another vector element"]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f64)"]
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
4657+
#[rustc_legacy_const_generics(1, 3)]
4658+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4659+
pub fn vcopy_laneq_f64<const LANE1: i32, const LANE2: i32>(
4660+
_a: float64x1_t,
4661+
b: float64x2_t,
4662+
) -> float64x1_t {
4663+
static_assert!(LANE1 == 0);
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static_assert_uimm_bits!(LANE2, 1);
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unsafe { transmute::<f64, _>(simd_extract!(b, LANE2 as u32)) }
4666+
}
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#[doc = "Insert vector element from another vector element"]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s64)"]
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
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#[rustc_legacy_const_generics(1, 3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4674+
pub fn vcopy_laneq_s64<const LANE1: i32, const LANE2: i32>(
4675+
_a: int64x1_t,
4676+
b: int64x2_t,
4677+
) -> int64x1_t {
4678+
static_assert!(LANE1 == 0);
4679+
static_assert_uimm_bits!(LANE2, 1);
4680+
unsafe { transmute::<i64, _>(simd_extract!(b, LANE2 as u32)) }
4681+
}
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#[doc = "Insert vector element from another vector element"]
4683+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u64)"]
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#[inline]
4685+
#[target_feature(enable = "neon")]
4686+
#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
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#[rustc_legacy_const_generics(1, 3)]
4688+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4689+
pub fn vcopy_laneq_u64<const LANE1: i32, const LANE2: i32>(
4690+
_a: uint64x1_t,
4691+
b: uint64x2_t,
4692+
) -> uint64x1_t {
4693+
static_assert!(LANE1 == 0);
4694+
static_assert_uimm_bits!(LANE2, 1);
4695+
unsafe { transmute::<u64, _>(simd_extract!(b, LANE2 as u32)) }
4696+
}
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#[doc = "Insert vector element from another vector element"]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p64)"]
4699+
#[inline]
4700+
#[target_feature(enable = "neon")]
4701+
#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
4702+
#[rustc_legacy_const_generics(1, 3)]
4703+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4704+
pub fn vcopy_laneq_p64<const LANE1: i32, const LANE2: i32>(
4705+
_a: poly64x1_t,
4706+
b: poly64x2_t,
4707+
) -> poly64x1_t {
4708+
static_assert!(LANE1 == 0);
4709+
static_assert_uimm_bits!(LANE2, 1);
4710+
unsafe { transmute::<u64, _>(simd_extract!(b, LANE2 as u32)) }
4711+
}
4712+
#[doc = "Insert vector element from another vector element"]
45844713
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)"]
45854714
#[inline]
45864715
#[target_feature(enable = "neon")]
@@ -11318,6 +11447,35 @@ pub fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
1131811447
pub fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
1131911448
vfmad_laneq_f64::<LANE>(a, -b, c)
1132011449
}
11450+
#[doc = "Duplicate vector element to vector or scalar"]
11451+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f64)"]
11452+
#[inline]
11453+
#[target_feature(enable = "neon")]
11454+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11455+
#[cfg_attr(test, assert_instr(fmov))]
11456+
pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
11457+
unsafe { float64x1_t([simd_extract!(a, 1)]) }
11458+
}
11459+
#[doc = "Duplicate vector element to vector or scalar"]
11460+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f64)"]
11461+
#[inline]
11462+
#[target_feature(enable = "neon")]
11463+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11464+
#[cfg_attr(test, assert_instr(nop))]
11465+
pub fn vget_low_f64(a: float64x2_t) -> float64x1_t {
11466+
unsafe { float64x1_t([simd_extract!(a, 0)]) }
11467+
}
11468+
#[doc = "Duplicate vector element to vector or scalar"]
11469+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f64)"]
11470+
#[inline]
11471+
#[target_feature(enable = "neon")]
11472+
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11473+
#[rustc_legacy_const_generics(1)]
11474+
#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
11475+
pub fn vgetq_lane_f64<const IMM5: i32>(a: float64x2_t) -> f64 {
11476+
static_assert_uimm_bits!(IMM5, 1);
11477+
unsafe { simd_extract!(a, IMM5 as u32) }
11478+
}
1132111479
#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
1132211480
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
1132311481
#[doc = "## Safety"]

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